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authorChaotian Jing <chaotian.jing@mediatek.com>2018-09-29 10:29:54 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2018-10-08 12:53:24 +0200
commit716b717ac07de239c6ad7bd3c38f2ef979280595 (patch)
tree06989cadaf021efe6449c60471ffcc37e2b6721e
parent32b64b0397b440877c4707f3cc3f5b4494f0be3e (diff)
downloadlinux-716b717ac07de239c6ad7bd3c38f2ef979280595.tar.bz2
mmc: dt-bindings: add "bus-clk" for MT2712
On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together, or will hang when access MSDC register. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/mmc/mtk-sd.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index f33467a54a05..f2208f4dcca8 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -22,6 +22,7 @@ Required properties:
"source" - source clock (required)
"hclk" - HCLK which used for host (required)
"source_cg" - independent source clock gate (required for MT2712)
+ "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl