diff options
| author | Marek Vasut <marex@denx.de> | 2022-10-31 21:48:38 +0100 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2022-11-22 00:04:49 +0200 |
| commit | 6a11d3a00dc1f152e8cdf97171128c4186695a9d (patch) | |
| tree | 19579595d22eb20da49d13246c78e11a11fdda87 | |
| parent | f8aa5f6dc1cb71d472d023f87d05f53b1672983f (diff) | |
| download | linux-6a11d3a00dc1f152e8cdf97171128c4186695a9d.tar.bz2 | |
clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x
The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used
to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz,
the PLL3 output can be divided down to supply UARTn_ROOT clock with
precise 64 MHz, which divided down further by 16x oversampling factor
used by the i.MX UART core yields 4 Mbdps baud base for the UART IP.
This is useful e.g. for BCM bluetooth chips, which can operate up to
4 Mbdps.
Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221031204838.195292-1-marex@denx.de
| -rw-r--r-- | drivers/clk/imx/clk-pll14xx.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1d0f79e9c346..828336873a98 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(800000000U, 200, 3, 1), PLL_1416X_RATE(750000000U, 250, 2, 2), PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(320000000U, 160, 3, 2), }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { |