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| author | Andrzej Hajda <a.hajda@samsung.com> | 2017-01-20 07:52:19 +0100 |
|---|---|---|
| committer | Inki Dae <inki.dae@samsung.com> | 2017-02-07 13:52:49 +0900 |
| commit | 648225880264fde99eba8e57f6ac81801be1405d (patch) | |
| tree | aa0025bd3bc8d4e0a8152c8a324faad2e042f8f0 | |
| parent | d796ddc9ea0c88f7a1cc1e8df10553f8bbc6ba6b (diff) | |
| download | linux-648225880264fde99eba8e57f6ac81801be1405d.tar.bz2 | |
drm/exynos/hdmi: add 297MHz pixel clock support
297MHz is used by Ultra HD modes.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_hdmi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 5ed8b1effe71..bef8965c9f53 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -587,6 +587,15 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = { 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, }, }, + { + .pixel_clock = 297000000, + .conf = { + 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2, + 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, + 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, + 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, + }, + }, }; static const char * const hdmi_clk_gates4[] = { |