drm/amd/display: Enable DCN clock gating

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 53 insertions, 19 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 62a77f48d437..24c1a0f5febe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -516,12 +516,14 @@ static void power_on_plane(
 	/* disable clock power gating */
 
 	/* DCCG_GATE_DISABLE_CNTL only has one instance */
-	HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
-			DISPCLK_DCCG_GATE_DISABLE, 1,
-			DPPCLK_GATE_DISABLE, 1);
-	/* DCFCLK_CNTL only has one instance */
-	HWSEQ_REG_UPDATE(DCFCLK_CNTL,
-			DCFCLK_GATE_DIS, 1);
+	if (ctx->dc->debug.disable_clock_gate) {
+		HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
+				DISPCLK_DCCG_GATE_DISABLE, 1,
+				DPPCLK_GATE_DISABLE, 1);
+		/* DCFCLK_CNTL only has one instance */
+		HWSEQ_REG_UPDATE(DCFCLK_CNTL,
+				DCFCLK_GATE_DIS, 1);
+	}
 
 	HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
 			IP_REQUEST_EN, 1);
@@ -533,14 +535,6 @@ static void power_on_plane(
 	if (ctx->dc->debug.disable_clock_gate) {
 		HWSEQ_REG_UPDATE(DCCG_GATE_DISABLE_CNTL,
 				DISPCLK_DCCG_GATE_DISABLE, 0);
-	} else {
-		/* DCCG_GATE_DISABLE_CNTL only has one instance. inst_offset = 0 */
-		HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
-				DISPCLK_DCCG_GATE_DISABLE, 0,
-				DPPCLK_GATE_DISABLE, 0);
-		/* DCFCLK_CNTL only has one instance. inst_offset = 0 */
-		HWSEQ_REG_UPDATE(DCFCLK_CNTL,
-				DCFCLK_GATE_DIS, 0);
 	}
 }
 
@@ -666,14 +660,58 @@ static void init_hw(struct core_dc *dc)
 			FD(DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE), 0,
 			FD(DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE), 0);
 
+	if (!dc->public.debug.disable_clock_gate) {
+		/* enable all DCN clock gating */
+		generic_reg_set_soc15(dc->ctx, 0, DCCG_GATE_DISABLE_CNTL, 19,
+				FD(DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE), 0);
+
+		generic_reg_set_soc15(dc->ctx, 0, DCCG_GATE_DISABLE_CNTL2, 14,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE), 0,
+				FD(DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE), 0);
+
+		generic_reg_update_soc15(dc->ctx, 0, DCFCLK_CNTL, 1,
+				FD(DCFCLK_CNTL__DCFCLK_GATE_DIS), 0);
+	}
+
 	/* This power gating should be one-time program for DAL.
 	 * It can only change by registry key
 	 * TODO: new task will for this.
 	 * if power gating is disable, power_on_plane and power_off_plane
 	 * should be skip. Otherwise, hand will be met in power_off_plane
 	 */
-
 	enable_power_gating_plane(dc->ctx, true);
+
+
 }
 
 static enum dc_status dcn10_prog_pixclk_crtc_otg(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 94cd7a9b0b19..660cb43fd3bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -426,8 +426,6 @@ static const struct resource_caps res_cap = {
 
 static const struct dc_debug debug_defaults_drv = {
 		.disable_dcc = false,
-		.disable_dpp_power_gate = false,
-		.disable_hubp_power_gate = false,
 		.disable_dmcu = true,
 		.force_abm_enable = false,
 		.timing_trace = false,
@@ -440,8 +438,6 @@ static const struct dc_debug debug_defaults_drv = {
 };
 
 static const struct dc_debug debug_defaults_diags = {
-		.disable_dpp_power_gate = false,
-		.disable_hubp_power_gate = false,
 		.disable_clock_gate = true,
 		.disable_dmcu = true,
 		.force_abm_enable = false,