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| author | Oak Zeng <Oak.Zeng@amd.com> | 2020-09-17 23:04:29 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 22:58:47 -0400 |
| commit | 522510a677953bbb37916b2090a604beb0fd063b (patch) | |
| tree | 4a0185834b3bd7ef6f2c110f6ba9af5d68e88325 | |
| parent | a2902c09c51db02eeffd77485c1340fdf4536af5 (diff) | |
| download | linux-522510a677953bbb37916b2090a604beb0fd063b.tar.bz2 | |
drm/amdgpu: Set up vmid0 PDB0
If use gart for FB translation, allocate and fill
PDB0.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 96052dc114cd..adc910a6dd19 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1379,7 +1379,16 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) adev->gart.table_size = adev->gart.num_gpu_pages * 8; adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | AMDGPU_PTE_EXECUTABLE; - return amdgpu_gart_table_vram_alloc(adev); + + r = amdgpu_gart_table_vram_alloc(adev); + if (r) + return r; + + if (adev->gmc.xgmi.connected_to_cpu) { + r = amdgpu_gmc_pdb0_alloc(adev); + } + + return r; } /** @@ -1566,6 +1575,8 @@ static int gmc_v9_0_sw_fini(void *handle) amdgpu_gart_table_vram_free(adev); amdgpu_bo_fini(adev); amdgpu_gart_fini(adev); + if (adev->gmc.pdb0_bo) + amdgpu_bo_unref(&adev->gmc.pdb0_bo); return 0; } @@ -1624,10 +1635,14 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) { int r; + if (adev->gmc.xgmi.connected_to_cpu) + amdgpu_gmc_init_pdb0(adev); + if (adev->gart.bo == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; } + r = amdgpu_gart_table_vram_pin(adev); if (r) return r; @@ -1640,9 +1655,14 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) if (r) return r; - DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", - (unsigned)(adev->gmc.gart_size >> 20), - (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); + DRM_INFO("PCIE GART of %uM enabled.\n", + (unsigned)(adev->gmc.gart_size >> 20)); + if (adev->gmc.pdb0_bo) + DRM_INFO("PDB0 located at 0x%016llX\n", + (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); + DRM_INFO("PTB located at 0x%016llX\n", + (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); + adev->gart.ready = true; return 0; } |