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| author | Lukas Bulwahn <lukas.bulwahn@gmail.com> | 2020-08-19 10:18:08 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-24 12:23:02 -0400 |
| commit | 5049a0526988d575c777db20a52eba5efaadbd2a (patch) | |
| tree | 5e447ce4f1b907ca8ca08ba5ca4970ae2a7b684f | |
| parent | 53b3f8f40e6cff36ae12b11e6d6b308af3c7e53f (diff) | |
| download | linux-5049a0526988d575c777db20a52eba5efaadbd2a.tar.bz2 | |
drm/amd/display: remove unintended executable mode
Besides the intended change, commit 4cc1178e166a ("drm/amdgpu: replace DRM
prefix with PCI device info for gfx/mmhub") also set the source files
mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode
644 to new mode 755.
Commit 241b2ec9317e ("drm/amd/display: Add dcn30 Headers (v2)") added the
four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e.,
mode 755.
Set to the usual modes for source and headers files and clean up those
mistakes. No functional change.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h | 0 |
6 files changed, 0 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c index 46351db36922..46351db36922 100755..100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 45a902b1acb7..45a902b1acb7 100755..100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index cf166b591bc5..cf166b591bc5 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h index ea683f452bb3..ea683f452bb3 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h index 67faaf68e9d7..67faaf68e9d7 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h index b4ef50a72868..b4ef50a72868 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h |