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authorCatalin Marinas <catalin.marinas@arm.com>2013-11-29 10:56:14 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2013-11-29 15:05:07 +0000
commit4f00130b70e5eee813cc7bc298e0f3fdf79673cc (patch)
treeff4efdbf6eabe114e59c979949bbaa9324065c50
parent2dacab73dc9f86ad12eb41bc3355d7f492696bca (diff)
downloadlinux-4f00130b70e5eee813cc7bc298e0f3fdf79673cc.tar.bz2
arm64: Use Normal NonCacheable memory for writecombine
This provides better performance compared to Device GRE and also allows unaligned accesses. Such memory is intended to be used with standard RAM (e.g. framebuffers) and not I/O. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r--arch/arm64/include/asm/pgtable.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 17bd3af0a117..5347b39fdb35 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -254,7 +254,7 @@ static inline int has_transparent_hugepage(void)
#define pgprot_noncached(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
#define pgprot_writecombine(prot) \
- __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE))
+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
#define pgprot_dmacoherent(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
#define __HAVE_PHYS_MEM_ACCESS_PROT