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authorRoger Quadros <rogerq@ti.com>2019-10-28 11:37:30 +0200
committerTero Kristo <t-kristo@ti.com>2019-11-08 11:41:54 +0200
commit49e19745e4b55ceb5d4d9199a5860044284f5c69 (patch)
tree4d8dfc0577d5aee1de825e0041c3da3d01be0420
parent451555c80bc66551278d92575030fab6bf04641c (diff)
downloadlinux-49e19745e4b55ceb5d4d9199a5860044284f5c69.tar.bz2
arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
Add USB0 as otg port and USB1 as host port. Although USB0 can be used at super-speed, limit the speed to high-speed for now till SERDES PHY support is added. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts35
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 57df79a815f0..2a3cd6174504 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -55,6 +55,18 @@
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
+
+ main_usbss0_pins_default: main_usbss0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ >;
+ };
+
+ main_usbss1_pins_default: main_usbss1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -244,3 +256,26 @@
/* Unused */
status = "disabled";
};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,usb2-only;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>;
+ ti,usb2-only;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};