diff options
| author | Eric Bernstein <eric.bernstein@amd.com> | 2022-03-03 14:11:46 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:43:38 -0400 |
| commit | 2cb6915dcf70a2bf7ee10fcf3f56b083beec1086 (patch) | |
| tree | e80b7035c35041af466b35b7655355341f1c965f | |
| parent | 3dc35cf8789ac93d656f255539f9b37c5051ebf6 (diff) | |
| download | linux-2cb6915dcf70a2bf7ee10fcf3f56b083beec1086.tar.bz2 | |
drm/amd/display: Use DTBCLK for valid pixel clock
Use DTBCLK for valid pixel clock generation
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Acked-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 17 |
2 files changed, 31 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 5609ac6d6040..b78775e8c13c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -42,12 +42,6 @@ #define DC_LOGGER \ dccg->ctx->logger -enum pixel_rate_div { - PIXEL_RATE_DIV_BY_1 = 0, - PIXEL_RATE_DIV_BY_2 = 1, - PIXEL_RATE_DIV_BY_4 = 3 -}; - static void dccg32_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, @@ -183,6 +177,19 @@ void dccg32_set_dtbclk_dto( } } +void dccg32_set_valid_pixel_rate( + struct dccg *dccg, + int otg_inst, + int pixclk_khz) +{ + struct dtbclk_dto_params dto_params = {0}; + + dto_params.otg_inst = otg_inst; + dto_params.pixclk_khz = pixclk_khz; + + dccg32_set_dtbclk_dto(dccg, &dto_params); +} + static void dccg32_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz) @@ -260,6 +267,7 @@ static const struct dccg_funcs dccg32_funcs = { .disable_symclk32_le = dccg31_disable_symclk32_le, .set_physymclk = dccg31_set_physymclk, .set_dtbclk_dto = dccg32_set_dtbclk_dto, + .set_valid_pixel_rate = dccg32_set_valid_pixel_rate, .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, .otg_add_pixel = dccg32_otg_add_pixel, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index b5acc6b9f3c9..8b450a7274ae 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -56,6 +56,12 @@ enum dentist_dispclk_change_mode { DISPCLK_CHANGE_MODE_RAMPING, }; +enum pixel_rate_div { + PIXEL_RATE_DIV_BY_1 = 0, + PIXEL_RATE_DIV_BY_2 = 1, + PIXEL_RATE_DIV_BY_4 = 3 +}; + struct dccg { struct dc_context *ctx; const struct dccg_funcs *funcs; @@ -139,6 +145,17 @@ struct dccg_funcs { struct dccg *dccg, int inst); +void (*set_pixel_rate_div)( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div k1, + enum pixel_rate_div k2); + +void (*set_valid_pixel_rate)( + struct dccg *dccg, + int otg_inst, + int pixclk_khz); + }; #endif //__DAL_DCCG_H__ |