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| author | Thomas Gleixner <tglx@linutronix.de> | 2022-02-13 14:16:23 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2022-02-13 14:16:23 +0100 |
| commit | 1e34064b60552616b2767d22f2e6f440ced09acb (patch) | |
| tree | 463e5adfb5550ce20ebfc8081af6688d228d7336 | |
| parent | dd7f5a11ac5a6f733f422dc22b4d145d3260304e (diff) | |
| parent | 1d4df649cbb4b26d19bea38ecff4b65b10a1bbca (diff) | |
| download | linux-1e34064b60552616b2767d22f2e6f440ced09acb.tar.bz2 | |
Merge tag 'irqchip-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier:
- Don't register a hotplug notifier on GICv3 systems that advertise
LPI support, but have no ITS to make use of it
- Add missing DT matching for the thead,c900-plic variant of the
SiFive PLIC
Link: https://lore.kernel.org/r/20220211110038.1179155-1-maz@kernel.org
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 21 | ||||
| -rw-r--r-- | drivers/irqchip/irq-gic-v3-its.c | 3 | ||||
| -rw-r--r-- | drivers/irqchip/irq-sifive-plic.c | 1 |
3 files changed, 19 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0dfa6b26e099..27092c6a86c4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -35,6 +35,10 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the + T-HEAD PLIC implementation requires setting a delegation bit to allow access + from S-mode. So add thead,c900-plic to distinguish them. + maintainers: - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> @@ -42,12 +46,17 @@ maintainers: properties: compatible: - items: - - enum: - - sifive,fu540-c000-plic - - starfive,jh7100-plic - - canaan,k210-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: + - enum: + - allwinner,sun20i-d1-plic + - const: thead,c900-plic reg: maxItems: 1 diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 9e93ff2b6375..cd772973114a 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -5517,6 +5517,9 @@ int __init its_lpi_memreserve_init(void) if (!efi_enabled(EFI_CONFIG_TABLES)) return 0; + if (list_empty(&its_nodes)) + return 0; + gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "irqchip/arm/gicv3/memreserve:online", diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 259065d271ef..09cc98266d30 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -398,3 +398,4 @@ out_free_priv: IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */ |