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authorThomas Voegtle <tv@lio96.de>2019-07-20 19:01:22 +0200
committerDavid S. Miller <davem@davemloft.net>2019-07-20 12:17:45 -0700
commit1a03bb532934e90c7d662f7c59f4f66ea8451fa4 (patch)
tree1fafdcf5d1e71763effa4c521c287c366d9475c4
parent89099d855bf084c3e428ca257b50d77d1a468437 (diff)
downloadlinux-1a03bb532934e90c7d662f7c59f4f66ea8451fa4.tar.bz2
r8169: fix RTL8168g PHY init
This fixes a copy&paste error in the original patch. Setting the wrong register resulted in massive packet loss on some systems. Fixes: a2928d28643e ("r8169: use paged versions of phylib MDIO access functions") Tested-by: Thomas Voegtle <tv@lio96.de> Signed-off-by: Thomas Voegtle <tv@lio96.de> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/realtek/r8169_main.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 0637c6752a78..6272115b2848 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -3251,9 +3251,9 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
if (ret & BIT(8))
- phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
+ phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
else
- phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
+ phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
/* Enable PHY auto speed down */
phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));