diff options
| author | Yash Shah <yash.shah@sifive.com> | 2020-01-07 22:09:06 -0800 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2020-01-12 10:12:44 -0800 |
| commit | 13cf4cf030183dd9a8731f3fe32456e83b6c7b68 (patch) | |
| tree | 8e38c8d3ceffe43b178df93bb14b36f0b4d1dcec | |
| parent | c79f46a282390e0f5b306007bf7b11a46d529538 (diff) | |
| download | linux-13cf4cf030183dd9a8731f3fe32456e83b6c7b68.tar.bz2 | |
riscv: move sifive_l2_cache.h to include/soc
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: updated to fix the include guard]
Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
| -rw-r--r-- | drivers/edac/sifive_edac.c | 2 | ||||
| -rw-r--r-- | drivers/soc/sifive/sifive_l2_cache.c | 2 | ||||
| -rw-r--r-- | include/soc/sifive/sifive_l2_cache.h (renamed from arch/riscv/include/asm/sifive_l2_cache.h) | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index 413cdb4a591d..c0cc72a3b2be 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -10,7 +10,7 @@ #include <linux/edac.h> #include <linux/platform_device.h> #include "edac_module.h" -#include <asm/sifive_l2_cache.h> +#include <soc/sifive/sifive_l2_cache.h> #define DRVNAME "sifive_edac" diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a9ffff3277c7..a5069394cd61 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,7 +9,7 @@ #include <linux/interrupt.h> #include <linux/of_irq.h> #include <linux/of_address.h> -#include <asm/sifive_l2_cache.h> +#include <soc/sifive/sifive_l2_cache.h> #define SIFIVE_L2_DIRECCFIX_LOW 0x100 #define SIFIVE_L2_DIRECCFIX_HIGH 0x104 diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h index 04f6748fc50b..92ade10ed67e 100644 --- a/arch/riscv/include/asm/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_l2_cache.h @@ -4,8 +4,8 @@ * */ -#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H -#define _ASM_RISCV_SIFIVE_L2_CACHE_H +#ifndef __SOC_SIFIVE_L2_CACHE_H +#define __SOC_SIFIVE_L2_CACHE_H extern int register_sifive_l2_error_notifier(struct notifier_block *nb); extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); @@ -13,4 +13,4 @@ extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); #define SIFIVE_L2_ERR_TYPE_CE 0 #define SIFIVE_L2_ERR_TYPE_UE 1 -#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */ +#endif /* __SOC_SIFIVE_L2_CACHE_H */ |