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| author | Robert Jarzmik <robert.jarzmik@free.fr> | 2014-07-30 22:51:01 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-09-30 12:31:31 -0700 |
| commit | 108f303f0ed92549b061e08a18361ad4bd540b27 (patch) | |
| tree | d2351bf8d0f576d4ea0cc18ccf6b7a4376939331 | |
| parent | 53f3394a0fe97420ec260e4dad7854add90a66dd (diff) | |
| download | linux-108f303f0ed92549b061e08a18361ad4bd540b27.tar.bz2 | |
arm: pxa: add clock pll selection bits
Add missing bits for CCCR and CCSR :
- CPLL and PPLL selection, either full speed or 13MHz
- CPSR masks
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index ee6ced1cea7f..f1dd62946b36 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -143,6 +143,16 @@ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ +#define CCCR_CPDIS_BIT (31) +#define CCCR_PPDIS_BIT (30) +#define CCCR_LCD_26_BIT (27) +#define CCCR_A_BIT (25) + +#define CCSR_N2_MASK CCCR_N_MASK +#define CCSR_M_MASK CCCR_M_MASK +#define CCSR_L_MASK CCCR_L_MASK +#define CCSR_N2_SHIFT 7 + #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ |