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authorPhil Edworthy <phil.edworthy@renesas.com>2022-04-22 20:06:15 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2022-04-26 13:25:47 +0200
commit070e246217230cce21b8dddad38bd59428494c48 (patch)
tree66caa5e770105d9bf03e7b9b67e401f789e0b72d
parentaa63d786cea2739791032742efc11990ce32ee4a (diff)
downloadlinux-070e246217230cce21b8dddad38bd59428494c48.tar.bz2
serial: 8250: dw: Improve RZN1 support
Renesas RZ/N1 SoC features a slightly modified DW UART. On this SoC, the CPR register value is known but not synthetized in hardware. We hence need to provide a CPR value in the platform data. This version of the controller also relies on acting as flow controller when using DMA, so we need to provide the "is dma flow controller" quirk. Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220422180615.9098-10-miquel.raynal@bootlin.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/tty/serial/8250/8250_dw.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 90e64c8bd4bf..0cf1a99dc124 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -761,6 +761,8 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
.usr_reg = DW_UART_USR,
+ .cpr_val = 0x00012f32,
+ .quirks = DW_UART_QUIRK_IS_DMA_FC,
};
static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {