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| author | Douglas Anderson <dianders@chromium.org> | 2020-12-10 10:22:39 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-12-10 12:27:30 -0800 |
| commit | 043577518f027544e8f9e9568140a1fe87ee01a0 (patch) | |
| tree | be6280acf2d4fdc2f61186dd8a68bde9d46463f9 | |
| parent | 6d37a8d192830267e6b10a6d57ae28d2e89097e7 (diff) | |
| download | linux-043577518f027544e8f9e9568140a1fe87ee01a0.tar.bz2 | |
clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
50 MHz is an incredibly common clock rate for SD cards to run at.
It's "high speed" mode in SD (not very fast these days, but it used to
be) or:
#define HIGH_SPEED_MAX_DTR 50000000
If we don't support this then older "high speed" cards can only run at
25 MHz or at half their normal speed. There doesn't seem to be any
reason to skip this clock rate, so add it.
Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeid
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/qcom/gcc-sc7180.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index b080739ab0c3..d82d725ac231 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -651,6 +651,7 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), { } |