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authorPaul Mackerras <paulus@samba.org>2013-09-20 14:52:46 +1000
committerAlexander Graf <agraf@suse.de>2013-10-17 14:45:04 +0200
commit03a9c90334d611c3006ac9569579f25f64812bc1 (patch)
tree8bac356754c5a13b47a15f8a7d7b8726a42b5d38
parentc9029c341da646ab0c9911ea4c118eaa0a2eb0fa (diff)
downloadlinux-03a9c90334d611c3006ac9569579f25f64812bc1.tar.bz2
KVM: PPC: Book3S PR: Handle PP0 page-protection bit in guest HPTEs
64-bit POWER processors have a three-bit field for page protection in the hashed page table entry (HPTE). Currently we only interpret the two bits that were present in older versions of the architecture. The only defined combination that has the new bit set is 110, meaning read-only for supervisor and no access for user mode. This adds code to kvmppc_mmu_book3s_64_xlate() to interpret the extra bit appropriately. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r--arch/powerpc/kvm/book3s_64_mmu.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c
index ffcde01cb995..9e6e11270b70 100644
--- a/arch/powerpc/kvm/book3s_64_mmu.c
+++ b/arch/powerpc/kvm/book3s_64_mmu.c
@@ -298,6 +298,8 @@ do_second:
v = pteg[i];
r = pteg[i+1];
pp = (r & HPTE_R_PP) | key;
+ if (r & HPTE_R_PP0)
+ pp |= 8;
gpte->eaddr = eaddr;
gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data);
@@ -319,6 +321,7 @@ do_second:
case 3:
case 5:
case 7:
+ case 10:
gpte->may_read = true;
break;
}