ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls

The function of each SoM pins is defined in the DHCOM standard [1] and
subset of them is defined as GPIOs (pins A-W). To ensure the interchange-
ability of the DHCOM SoMs, the function of the pins are fixed and cannot
be changed. On board level the DHCOM GPIOs can be used associated with
different blocks e.g. for interrupt or reset, but the function is always
GPIO. If not used, they can be freely used in the user space.

Therefore the whole configuration of SoM pins is made in the SoM DT.
Defining the DHCOM GPIO pins as a separate pinctrl nodes makes moving a
subset of them to an appropriate block pinctrl group easier on board level,
since it is not necessary to have a large pinctrl hog group containing
unrelated pinmux entries on board level. This also makes it easy to update
the SoM DT without having to update all the board DTs too. If necessary it
is also possible to change the electrical properties of the DHCOM GPIOs by
overwriting the pinctrl on board level.

[1] https://wiki.dh-electronics.com/images/2/2e/DOC_DHCOM-Standard-Specification_R01_2016-11-17.pdf

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

2 files changed, 148 insertions, 66 deletions

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 3ed93a8e98fe..3ea077ec8606 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -38,7 +38,7 @@
 		#size-cells = <0>;
 		interface-pix-fmt = "rgb24";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
 		status = "okay";
 
 		port@0 {
@@ -61,13 +61,13 @@
 	gpio-keys {
 		#size-cells = <0>;
 		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_keys_pdk2>;
 
 		button-0 {
 			label = "TA1-GPIO-A";
 			linux,code = <KEY_A>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_a>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 
@@ -75,6 +75,8 @@
 			label = "TA2-GPIO-B";
 			linux,code = <KEY_B>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_b>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 
@@ -82,6 +84,8 @@
 			label = "TA3-GPIO-C";
 			linux,code = <KEY_C>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_c>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 
@@ -89,14 +93,14 @@
 			label = "TA4-GPIO-D";
 			linux,code = <KEY_D>;
 			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
+			pinctrl-0 = <&pinctrl_dhcom_d>;
+			pinctrl-names = "default";
 			wakeup-source;
 		};
 	};
 
 	led {
 		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_leds_pdk2>;
 
 		/*
 		 * Disable led-5, because GPIO E is
@@ -107,6 +111,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_e>;
+			pinctrl-names = "default";
 			status = "disabled";
 		};
 
@@ -115,6 +121,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_f>;
+			pinctrl-names = "default";
 		};
 
 		led-7 {
@@ -122,6 +130,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_h>;
+			pinctrl-names = "default";
 		};
 
 		led-8 {
@@ -129,6 +139,8 @@
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
 			default-state = "off";
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
 		};
 	};
 
@@ -228,7 +240,7 @@
 
 	touchscreen@38 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_touchscreen>;
+		pinctrl-0 = <&pinctrl_dhcom_e>;
 		compatible = "edt,edt-ft5406";
 		reg = <0x38>;
 		interrupt-parent = <&gpio4>;
@@ -238,34 +250,28 @@
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
-
-	pinctrl_hog: hog-grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x400120b0
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x400120b0
-			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x400120b0
-			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x400120b0
-			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x400120b0
-			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0
-			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x400120b0
-			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x400120b0
-			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x400120b0
-			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x400120b0
-			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x400120b0
-			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x400120b0
-			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x400120b0
-			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x400120b0
-			MX6QDL_PAD_SD1_CMD__GPIO1_IO18		0x400120b0
-			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16		0x400120b0
-			MX6QDL_PAD_SD1_DAT1__GPIO1_IO17		0x400120b0
-			MX6QDL_PAD_SD1_DAT2__GPIO1_IO19		0x400120b0
-			MX6QDL_PAD_SD1_CLK__GPIO1_IO20		0x400120b0
-			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x400120b0
-			MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x400120b0
-			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x400120b0
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * A: key TA1
+			 * B: key TA2
+			 * C: key TA3
+			 * D: key TA4
+			 * E: touchscreen
+			 * F: led6
+			 * G: backlight enable
+			 * H: led7
+			 * I: led8
+			 * J: PCIe reset
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
 		>;
-	};
 
 	pinctrl_audmux_ext: audmux-ext-grp {
 		fsl,pins = <
@@ -334,7 +340,6 @@
 			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x38
 			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x38
 			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x38
-			MX6QDL_PAD_EIM_D27__GPIO3_IO27			0x120b0
 		>;
 	};
 
@@ -343,36 +348,6 @@
 			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
 		>;
 	};
-
-	pinctrl_touchscreen: touchscreen-grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b1
-		>;
-	};
-
-	pinctrl_pcie_reset: pcie-reset-grp {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0
-		>;
-	};
-
-	pinctrl_keys_pdk2: keys-pdk2-grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x120b0 /* TA1 */
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x120b0 /* TA2 */
-			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x120b0 /* TA3 */
-			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x120b0 /* TA4 */
-		>;
-	};
-
-	pinctrl_leds_pdk2: leds-pdk2-grp {
-		fsl,pins = <
-			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x120b0 /* led6 */
-			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x120b0 /* led7 */
-			MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x120b0 /* led8 */
-		>;
-	};
-
 };
 
 &ipu1_di0_disp0 {
@@ -380,7 +355,7 @@
 };
 
 &pcie {
-	pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;
+	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
 	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 688f04eeabc5..a361e161fba1 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -317,7 +317,17 @@
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog_base>;
+	pinctrl-0 = <
+			&pinctrl_hog_base
+			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+			&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
 
 	pinctrl_hog_base: hog-base-grp {
 		fsl,pins = <
@@ -329,6 +339,103 @@
 		>;
 	};
 
+	/* DHCOM GPIOs */
+	pinctrl_dhcom_a: dhcom-a-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x400120b0>;
+	};
+
+	pinctrl_dhcom_b: dhcom-b-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04	0x400120b0>;
+	};
+
+	pinctrl_dhcom_c: dhcom-c-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05	0x400120b0>;
+	};
+
+	pinctrl_dhcom_d: dhcom-d-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x400120b0>;
+	};
+
+	pinctrl_dhcom_e: dhcom-e-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05	0x400120b0>;
+	};
+
+	pinctrl_dhcom_f: dhcom-f-grp {
+		fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20	0x400120b0>;
+	};
+
+	pinctrl_dhcom_g: dhcom-g-grp {
+		fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27	0x400120b0>;
+	};
+
+	pinctrl_dhcom_h: dhcom-h-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07	0x400120b0>;
+	};
+
+	pinctrl_dhcom_i: dhcom-i-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08	0x400120b0>;
+	};
+
+	pinctrl_dhcom_j: dhcom-j-grp {
+		fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x400120b0>;
+	};
+
+	pinctrl_dhcom_k: dhcom-k-grp {
+		fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x400120b0>;
+	};
+
+	pinctrl_dhcom_l: dhcom-l-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09	0x400120b0>;
+	};
+
+	pinctrl_dhcom_m: dhcom-m-grp {
+		fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00	0x400120b0>;
+	};
+
+	pinctrl_dhcom_n: dhcom-n-grp {
+		fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01	0x400120b0>;
+	};
+
+	pinctrl_dhcom_o: dhcom-o-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x400120b0>;
+	};
+
+	pinctrl_dhcom_p: dhcom-p-grp {
+		fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13	0x400120b0>;
+	};
+
+	pinctrl_dhcom_q: dhcom-q-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18	0x400120b0>;
+	};
+
+	pinctrl_dhcom_r: dhcom-r-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16	0x400120b0>;
+	};
+
+	pinctrl_dhcom_s: dhcom-s-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17	0x400120b0>;
+	};
+
+	pinctrl_dhcom_t: dhcom-t-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19	0x400120b0>;
+	};
+
+	pinctrl_dhcom_u: dhcom-u-grp {
+		fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20	0x400120b0>;
+	};
+
+	pinctrl_dhcom_v: dhcom-v-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x400120b0>;
+	};
+
+	pinctrl_dhcom_w: dhcom-w-grp {
+		fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x400120b0>;
+	};
+
+	pinctrl_dhcom_int: dhcom-int-grp {
+		fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06	0x400120b0>;
+	};
+
 	pinctrl_ecspi1: ecspi1-grp {
 		fsl,pins = <
 			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1