summaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs/wsa881x.c
blob: b59f1d0e7f843d88079b1df0b8280867f88d2f05 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2015-2017, The Linux Foundation.
// Copyright (c) 2019, Linaro Limited

#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/soc.h>
#include <sound/tlv.h>

#define WSA881X_DIGITAL_BASE		0x3000
#define WSA881X_ANALOG_BASE		0x3100

/* Digital register address space */
#define WSA881X_CHIP_ID0			(WSA881X_DIGITAL_BASE + 0x0000)
#define WSA881X_CHIP_ID1			(WSA881X_DIGITAL_BASE + 0x0001)
#define WSA881X_CHIP_ID2			(WSA881X_DIGITAL_BASE + 0x0002)
#define WSA881X_CHIP_ID3			(WSA881X_DIGITAL_BASE + 0x0003)
#define WSA881X_BUS_ID				(WSA881X_DIGITAL_BASE + 0x0004)
#define WSA881X_CDC_RST_CTL			(WSA881X_DIGITAL_BASE + 0x0005)
#define WSA881X_CDC_TOP_CLK_CTL			(WSA881X_DIGITAL_BASE + 0x0006)
#define WSA881X_CDC_ANA_CLK_CTL			(WSA881X_DIGITAL_BASE + 0x0007)
#define WSA881X_CDC_DIG_CLK_CTL			(WSA881X_DIGITAL_BASE + 0x0008)
#define WSA881X_CLOCK_CONFIG			(WSA881X_DIGITAL_BASE + 0x0009)
#define WSA881X_ANA_CTL				(WSA881X_DIGITAL_BASE + 0x000A)
#define WSA881X_SWR_RESET_EN			(WSA881X_DIGITAL_BASE + 0x000B)
#define WSA881X_RESET_CTL			(WSA881X_DIGITAL_BASE + 0x000C)
#define WSA881X_TADC_VALUE_CTL			(WSA881X_DIGITAL_BASE + 0x000F)
#define WSA881X_TEMP_DETECT_CTL			(WSA881X_DIGITAL_BASE + 0x0010)
#define WSA881X_TEMP_MSB			(WSA881X_DIGITAL_BASE + 0x0011)
#define WSA881X_TEMP_LSB			(WSA881X_DIGITAL_BASE + 0x0012)
#define WSA881X_TEMP_CONFIG0			(WSA881X_DIGITAL_BASE + 0x0013)
#define WSA881X_TEMP_CONFIG1			(WSA881X_DIGITAL_BASE + 0x0014)
#define WSA881X_CDC_CLIP_CTL			(WSA881X_DIGITAL_BASE + 0x0015)
#define WSA881X_SDM_PDM9_LSB			(WSA881X_DIGITAL_BASE + 0x0016)
#define WSA881X_SDM_PDM9_MSB			(WSA881X_DIGITAL_BASE + 0x0017)
#define WSA881X_CDC_RX_CTL			(WSA881X_DIGITAL_BASE + 0x0018)
#define WSA881X_DEM_BYPASS_DATA0		(WSA881X_DIGITAL_BASE + 0x0019)
#define WSA881X_DEM_BYPASS_DATA1		(WSA881X_DIGITAL_BASE + 0x001A)
#define WSA881X_DEM_BYPASS_DATA2		(WSA881X_DIGITAL_BASE + 0x001B)
#define WSA881X_DEM_BYPASS_DATA3		(WSA881X_DIGITAL_BASE + 0x001C)
#define WSA881X_OTP_CTRL0			(WSA881X_DIGITAL_BASE + 0x001D)
#define WSA881X_OTP_CTRL1			(WSA881X_DIGITAL_BASE + 0x001E)
#define WSA881X_HDRIVE_CTL_GROUP1		(WSA881X_DIGITAL_BASE + 0x001F)
#define WSA881X_INTR_MODE			(WSA881X_DIGITAL_BASE + 0x0020)
#define WSA881X_INTR_MASK			(WSA881X_DIGITAL_BASE + 0x0021)
#define WSA881X_INTR_STATUS			(WSA881X_DIGITAL_BASE + 0x0022)
#define WSA881X_INTR_CLEAR			(WSA881X_DIGITAL_BASE + 0x0023)
#define WSA881X_INTR_LEVEL			(WSA881X_DIGITAL_BASE + 0x0024)
#define WSA881X_INTR_SET			(WSA881X_DIGITAL_BASE + 0x0025)
#define WSA881X_INTR_TEST			(WSA881X_DIGITAL_BASE + 0x0026)
#define WSA881X_PDM_TEST_MODE			(WSA881X_DIGITAL_BASE + 0x0030)
#define WSA881X_ATE_TEST_MODE			(WSA881X_DIGITAL_BASE + 0x0031)
#define WSA881X_PIN_CTL_MODE			(WSA881X_DIGITAL_BASE + 0x0032)
#define WSA881X_PIN_CTL_OE			(WSA881X_DIGITAL_BASE + 0x0033)
#define WSA881X_PIN_WDATA_IOPAD			(WSA881X_DIGITAL_BASE + 0x0034)
#define WSA881X_PIN_STATUS			(WSA881X_DIGITAL_BASE + 0x0035)
#define WSA881X_DIG_DEBUG_MODE			(WSA881X_DIGITAL_BASE + 0x0037)
#define WSA881X_DIG_DEBUG_SEL			(WSA881X_DIGITAL_BASE + 0x0038)
#define WSA881X_DIG_DEBUG_EN			(WSA881X_DIGITAL_BASE + 0x0039)
#define WSA881X_SWR_HM_TEST1			(WSA881X_DIGITAL_BASE + 0x003B)
#define WSA881X_SWR_HM_TEST2			(WSA881X_DIGITAL_BASE + 0x003C)
#define WSA881X_TEMP_DETECT_DBG_CTL		(WSA881X_DIGITAL_BASE + 0x003D)
#define WSA881X_TEMP_DEBUG_MSB			(WSA881X_DIGITAL_BASE + 0x003E)
#define WSA881X_TEMP_DEBUG_LSB			(WSA881X_DIGITAL_BASE + 0x003F)
#define WSA881X_SAMPLE_EDGE_SEL			(WSA881X_DIGITAL_BASE + 0x0044)
#define WSA881X_IOPAD_CTL			(WSA881X_DIGITAL_BASE + 0x0045)
#define WSA881X_SPARE_0				(WSA881X_DIGITAL_BASE + 0x0050)
#define WSA881X_SPARE_1				(WSA881X_DIGITAL_BASE + 0x0051)
#define WSA881X_SPARE_2				(WSA881X_DIGITAL_BASE + 0x0052)
#define WSA881X_OTP_REG_0			(WSA881X_DIGITAL_BASE + 0x0080)
#define WSA881X_OTP_REG_1			(WSA881X_DIGITAL_BASE + 0x0081)
#define WSA881X_OTP_REG_2			(WSA881X_DIGITAL_BASE + 0x0082)
#define WSA881X_OTP_REG_3			(WSA881X_DIGITAL_BASE + 0x0083)
#define WSA881X_OTP_REG_4			(WSA881X_DIGITAL_BASE + 0x0084)
#define WSA881X_OTP_REG_5			(WSA881X_DIGITAL_BASE + 0x0085)
#define WSA881X_OTP_REG_6			(WSA881X_DIGITAL_BASE + 0x0086)
#define WSA881X_OTP_REG_7			(WSA881X_DIGITAL_BASE + 0x0087)
#define WSA881X_OTP_REG_8			(WSA881X_DIGITAL_BASE + 0x0088)
#define WSA881X_OTP_REG_9			(WSA881X_DIGITAL_BASE + 0x0089)
#define WSA881X_OTP_REG_10			(WSA881X_DIGITAL_BASE + 0x008A)
#define WSA881X_OTP_REG_11			(WSA881X_DIGITAL_BASE + 0x008B)
#define WSA881X_OTP_REG_12			(WSA881X_DIGITAL_BASE + 0x008C)
#define WSA881X_OTP_REG_13			(WSA881X_DIGITAL_BASE + 0x008D)
#define WSA881X_OTP_REG_14			(WSA881X_DIGITAL_BASE + 0x008E)
#define WSA881X_OTP_REG_15			(WSA881X_DIGITAL_BASE + 0x008F)
#define WSA881X_OTP_REG_16			(WSA881X_DIGITAL_BASE + 0x0090)
#define WSA881X_OTP_REG_17			(WSA881X_DIGITAL_BASE + 0x0091)
#define WSA881X_OTP_REG_18			(WSA881X_DIGITAL_BASE + 0x0092)
#define WSA881X_OTP_REG_19			(WSA881X_DIGITAL_BASE + 0x0093)
#define WSA881X_OTP_REG_20			(WSA881X_DIGITAL_BASE + 0x0094)
#define WSA881X_OTP_REG_21			(WSA881X_DIGITAL_BASE + 0x0095)
#define WSA881X_OTP_REG_22			(WSA881X_DIGITAL_BASE + 0x0096)
#define WSA881X_OTP_REG_23			(WSA881X_DIGITAL_BASE + 0x0097)
#define WSA881X_OTP_REG_24			(WSA881X_DIGITAL_BASE + 0x0098)
#define WSA881X_OTP_REG_25			(WSA881X_DIGITAL_BASE + 0x0099)
#define WSA881X_OTP_REG_26			(WSA881X_DIGITAL_BASE + 0x009A)
#define WSA881X_OTP_REG_27			(WSA881X_DIGITAL_BASE + 0x009B)
#define WSA881X_OTP_REG_28			(WSA881X_DIGITAL_BASE + 0x009C)
#define WSA881X_OTP_REG_29			(WSA881X_DIGITAL_BASE + 0x009D)
#define WSA881X_OTP_REG_30			(WSA881X_DIGITAL_BASE + 0x009E)
#define WSA881X_OTP_REG_31			(WSA881X_DIGITAL_BASE + 0x009F)
#define WSA881X_OTP_REG_63			(WSA881X_DIGITAL_BASE + 0x00BF)

/* Analog Register address space */
#define WSA881X_BIAS_REF_CTRL			(WSA881X_ANALOG_BASE + 0x0000)
#define WSA881X_BIAS_TEST			(WSA881X_ANALOG_BASE + 0x0001)
#define WSA881X_BIAS_BIAS			(WSA881X_ANALOG_BASE + 0x0002)
#define WSA881X_TEMP_OP				(WSA881X_ANALOG_BASE + 0x0003)
#define WSA881X_TEMP_IREF_CTRL			(WSA881X_ANALOG_BASE + 0x0004)
#define WSA881X_TEMP_ISENS_CTRL			(WSA881X_ANALOG_BASE + 0x0005)
#define WSA881X_TEMP_CLK_CTRL			(WSA881X_ANALOG_BASE + 0x0006)
#define WSA881X_TEMP_TEST			(WSA881X_ANALOG_BASE + 0x0007)
#define WSA881X_TEMP_BIAS			(WSA881X_ANALOG_BASE + 0x0008)
#define WSA881X_TEMP_ADC_CTRL			(WSA881X_ANALOG_BASE + 0x0009)
#define WSA881X_TEMP_DOUT_MSB			(WSA881X_ANALOG_BASE + 0x000A)
#define WSA881X_TEMP_DOUT_LSB			(WSA881X_ANALOG_BASE + 0x000B)
#define WSA881X_ADC_EN_MODU_V			(WSA881X_ANALOG_BASE + 0x0010)
#define WSA881X_ADC_EN_MODU_I			(WSA881X_ANALOG_BASE + 0x0011)
#define WSA881X_ADC_EN_DET_TEST_V		(WSA881X_ANALOG_BASE + 0x0012)
#define WSA881X_ADC_EN_DET_TEST_I		(WSA881X_ANALOG_BASE + 0x0013)
#define WSA881X_ADC_SEL_IBIAS			(WSA881X_ANALOG_BASE + 0x0014)
#define WSA881X_ADC_EN_SEL_IBAIS		(WSA881X_ANALOG_BASE + 0x0015)
#define WSA881X_SPKR_DRV_EN			(WSA881X_ANALOG_BASE + 0x001A)
#define WSA881X_SPKR_DRV_GAIN			(WSA881X_ANALOG_BASE + 0x001B)
#define WSA881X_PA_GAIN_SEL_MASK		BIT(3)
#define WSA881X_PA_GAIN_SEL_REG			BIT(3)
#define WSA881X_PA_GAIN_SEL_DRE			0
#define WSA881X_SPKR_PAG_GAIN_MASK		GENMASK(7, 4)
#define WSA881X_SPKR_DAC_CTL			(WSA881X_ANALOG_BASE + 0x001C)
#define WSA881X_SPKR_DRV_DBG			(WSA881X_ANALOG_BASE + 0x001D)
#define WSA881X_SPKR_PWRSTG_DBG			(WSA881X_ANALOG_BASE + 0x001E)
#define WSA881X_SPKR_OCP_CTL			(WSA881X_ANALOG_BASE + 0x001F)
#define WSA881X_SPKR_OCP_MASK			GENMASK(7, 6)
#define WSA881X_SPKR_OCP_EN			BIT(7)
#define WSA881X_SPKR_OCP_HOLD			BIT(6)
#define WSA881X_SPKR_CLIP_CTL			(WSA881X_ANALOG_BASE + 0x0020)
#define WSA881X_SPKR_BBM_CTL			(WSA881X_ANALOG_BASE + 0x0021)
#define WSA881X_SPKR_MISC_CTL1			(WSA881X_ANALOG_BASE + 0x0022)
#define WSA881X_SPKR_MISC_CTL2			(WSA881X_ANALOG_BASE + 0x0023)
#define WSA881X_SPKR_BIAS_INT			(WSA881X_ANALOG_BASE + 0x0024)
#define WSA881X_SPKR_PA_INT			(WSA881X_ANALOG_BASE + 0x0025)
#define WSA881X_SPKR_BIAS_CAL			(WSA881X_ANALOG_BASE + 0x0026)
#define WSA881X_SPKR_BIAS_PSRR			(WSA881X_ANALOG_BASE + 0x0027)
#define WSA881X_SPKR_STATUS1			(WSA881X_ANALOG_BASE + 0x0028)
#define WSA881X_SPKR_STATUS2			(WSA881X_ANALOG_BASE + 0x0029)
#define WSA881X_BOOST_EN_CTL			(WSA881X_ANALOG_BASE + 0x002A)
#define WSA881X_BOOST_EN_MASK			BIT(7)
#define WSA881X_BOOST_EN			BIT(7)
#define WSA881X_BOOST_CURRENT_LIMIT		(WSA881X_ANALOG_BASE + 0x002B)
#define WSA881X_BOOST_PS_CTL			(WSA881X_ANALOG_BASE + 0x002C)
#define WSA881X_BOOST_PRESET_OUT1		(WSA881X_ANALOG_BASE + 0x002D)
#define WSA881X_BOOST_PRESET_OUT2		(WSA881X_ANALOG_BASE + 0x002E)
#define WSA881X_BOOST_FORCE_OUT			(WSA881X_ANALOG_BASE + 0x002F)
#define WSA881X_BOOST_LDO_PROG			(WSA881X_ANALOG_BASE + 0x0030)
#define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB	(WSA881X_ANALOG_BASE + 0x0031)
#define WSA881X_BOOST_RON_CTL			(WSA881X_ANALOG_BASE + 0x0032)
#define WSA881X_BOOST_LOOP_STABILITY		(WSA881X_ANALOG_BASE + 0x0033)
#define WSA881X_BOOST_ZX_CTL			(WSA881X_ANALOG_BASE + 0x0034)
#define WSA881X_BOOST_START_CTL			(WSA881X_ANALOG_BASE + 0x0035)
#define WSA881X_BOOST_MISC1_CTL			(WSA881X_ANALOG_BASE + 0x0036)
#define WSA881X_BOOST_MISC2_CTL			(WSA881X_ANALOG_BASE + 0x0037)
#define WSA881X_BOOST_MISC3_CTL			(WSA881X_ANALOG_BASE + 0x0038)
#define WSA881X_BOOST_ATEST_CTL			(WSA881X_ANALOG_BASE + 0x0039)
#define WSA881X_SPKR_PROT_FE_GAIN		(WSA881X_ANALOG_BASE + 0x003A)
#define WSA881X_SPKR_PROT_FE_CM_LDO_SET		(WSA881X_ANALOG_BASE + 0x003B)
#define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1	(WSA881X_ANALOG_BASE + 0x003C)
#define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2	(WSA881X_ANALOG_BASE + 0x003D)
#define WSA881X_SPKR_PROT_ATEST1		(WSA881X_ANALOG_BASE + 0x003E)
#define WSA881X_SPKR_PROT_ATEST2		(WSA881X_ANALOG_BASE + 0x003F)
#define WSA881X_SPKR_PROT_FE_VSENSE_VCM		(WSA881X_ANALOG_BASE + 0x0040)
#define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1	(WSA881X_ANALOG_BASE + 0x0041)
#define WSA881X_BONGO_RESRV_REG1		(WSA881X_ANALOG_BASE + 0x0042)
#define WSA881X_BONGO_RESRV_REG2		(WSA881X_ANALOG_BASE + 0x0043)
#define WSA881X_SPKR_PROT_SAR			(WSA881X_ANALOG_BASE + 0x0044)
#define WSA881X_SPKR_STATUS3			(WSA881X_ANALOG_BASE + 0x0045)

#define SWRS_SCP_FRAME_CTRL_BANK(m)		(0x60 + 0x10 * (m))
#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)	(0xE0 + 0x10 * (m))
#define SWR_SLV_MAX_REG_ADDR	0x390
#define SWR_SLV_START_REG_ADDR	0x40
#define SWR_SLV_MAX_BUF_LEN	20
#define BYTES_PER_LINE		12
#define SWR_SLV_RD_BUF_LEN	8
#define SWR_SLV_WR_BUF_LEN	32
#define SWR_SLV_MAX_DEVICES	2
#define WSA881X_MAX_SWR_PORTS   4
#define WSA881X_VERSION_ENTRY_SIZE 27
#define WSA881X_OCP_CTL_TIMER_SEC 2
#define WSA881X_OCP_CTL_TEMP_CELSIUS 25
#define WSA881X_OCP_CTL_POLL_TIMER_SEC 60

#define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
		 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
	.tlv.p = (tlv_array), \
	.info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
	.put = wsa881x_put_pa_gain, \
	.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }

static struct reg_default wsa881x_defaults[] = {
	{ WSA881X_CHIP_ID0, 0x00 },
	{ WSA881X_CHIP_ID1, 0x00 },
	{ WSA881X_CHIP_ID2, 0x00 },
	{ WSA881X_CHIP_ID3, 0x02 },
	{ WSA881X_BUS_ID, 0x00 },
	{ WSA881X_CDC_RST_CTL, 0x00 },
	{ WSA881X_CDC_TOP_CLK_CTL, 0x03 },
	{ WSA881X_CDC_ANA_CLK_CTL, 0x00 },
	{ WSA881X_CDC_DIG_CLK_CTL, 0x00 },
	{ WSA881X_CLOCK_CONFIG, 0x00 },
	{ WSA881X_ANA_CTL, 0x08 },
	{ WSA881X_SWR_RESET_EN, 0x00 },
	{ WSA881X_TEMP_DETECT_CTL, 0x01 },
	{ WSA881X_TEMP_MSB, 0x00 },
	{ WSA881X_TEMP_LSB, 0x00 },
	{ WSA881X_TEMP_CONFIG0, 0x00 },
	{ WSA881X_TEMP_CONFIG1, 0x00 },
	{ WSA881X_CDC_CLIP_CTL, 0x03 },
	{ WSA881X_SDM_PDM9_LSB, 0x00 },
	{ WSA881X_SDM_PDM9_MSB, 0x00 },
	{ WSA881X_CDC_RX_CTL, 0x7E },
	{ WSA881X_DEM_BYPASS_DATA0, 0x00 },
	{ WSA881X_DEM_BYPASS_DATA1, 0x00 },
	{ WSA881X_DEM_BYPASS_DATA2, 0x00 },
	{ WSA881X_DEM_BYPASS_DATA3, 0x00 },
	{ WSA881X_OTP_CTRL0, 0x00 },
	{ WSA881X_OTP_CTRL1, 0x00 },
	{ WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
	{ WSA881X_INTR_MODE, 0x00 },
	{ WSA881X_INTR_STATUS, 0x00 },
	{ WSA881X_INTR_CLEAR, 0x00 },
	{ WSA881X_INTR_LEVEL, 0x00 },
	{ WSA881X_INTR_SET, 0x00 },
	{ WSA881X_INTR_TEST, 0x00 },
	{ WSA881X_PDM_TEST_MODE, 0x00 },
	{ WSA881X_ATE_TEST_MODE, 0x00 },
	{ WSA881X_PIN_CTL_MODE, 0x00 },
	{ WSA881X_PIN_CTL_OE, 0x00 },
	{ WSA881X_PIN_WDATA_IOPAD, 0x00 },
	{ WSA881X_PIN_STATUS, 0x00 },
	{ WSA881X_DIG_DEBUG_MODE, 0x00 },
	{ WSA881X_DIG_DEBUG_SEL, 0x00 },
	{ WSA881X_DIG_DEBUG_EN, 0x00 },
	{ WSA881X_SWR_HM_TEST1, 0x08 },
	{ WSA881X_SWR_HM_TEST2, 0x00 },
	{ WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
	{ WSA881X_TEMP_DEBUG_MSB, 0x00 },
	{ WSA881X_TEMP_DEBUG_LSB, 0x00 },
	{ WSA881X_SAMPLE_EDGE_SEL, 0x0C },
	{ WSA881X_SPARE_0, 0x00 },
	{ WSA881X_SPARE_1, 0x00 },
	{ WSA881X_SPARE_2, 0x00 },
	{ WSA881X_OTP_REG_0, 0x01 },
	{ WSA881X_OTP_REG_1, 0xFF },
	{ WSA881X_OTP_REG_2, 0xC0 },
	{ WSA881X_OTP_REG_3, 0xFF },
	{ WSA881X_OTP_REG_4, 0xC0 },
	{ WSA881X_OTP_REG_5, 0xFF },
	{ WSA881X_OTP_REG_6, 0xFF },
	{ WSA881X_OTP_REG_7, 0xFF },
	{ WSA881X_OTP_REG_8, 0xFF },
	{ WSA881X_OTP_REG_9, 0xFF },
	{ WSA881X_OTP_REG_10, 0xFF },
	{ WSA881X_OTP_REG_11, 0xFF },
	{ WSA881X_OTP_REG_12, 0xFF },
	{ WSA881X_OTP_REG_13, 0xFF },
	{ WSA881X_OTP_REG_14, 0xFF },
	{ WSA881X_OTP_REG_15, 0xFF },
	{ WSA881X_OTP_REG_16, 0xFF },
	{ WSA881X_OTP_REG_17, 0xFF },
	{ WSA881X_OTP_REG_18, 0xFF },
	{ WSA881X_OTP_REG_19, 0xFF },
	{ WSA881X_OTP_REG_20, 0xFF },
	{ WSA881X_OTP_REG_21, 0xFF },
	{ WSA881X_OTP_REG_22, 0xFF },
	{ WSA881X_OTP_REG_23, 0xFF },
	{ WSA881X_OTP_REG_24, 0x03 },
	{ WSA881X_OTP_REG_25, 0x01 },
	{ WSA881X_OTP_REG_26, 0x03 },
	{ WSA881X_OTP_REG_27, 0x11 },
	{ WSA881X_OTP_REG_63, 0x40 },
	/* WSA881x Analog registers */
	{ WSA881X_BIAS_REF_CTRL, 0x6C },
	{ WSA881X_BIAS_TEST, 0x16 },
	{ WSA881X_BIAS_BIAS, 0xF0 },
	{ WSA881X_TEMP_OP, 0x00 },
	{ WSA881X_TEMP_IREF_CTRL, 0x56 },
	{ WSA881X_TEMP_ISENS_CTRL, 0x47 },
	{ WSA881X_TEMP_CLK_CTRL, 0x87 },
	{ WSA881X_TEMP_TEST, 0x00 },
	{ WSA881X_TEMP_BIAS, 0x51 },
	{ WSA881X_TEMP_DOUT_MSB, 0x00 },
	{ WSA881X_TEMP_DOUT_LSB, 0x00 },
	{ WSA881X_ADC_EN_MODU_V, 0x00 },
	{ WSA881X_ADC_EN_MODU_I, 0x00 },
	{ WSA881X_ADC_EN_DET_TEST_V, 0x00 },
	{ WSA881X_ADC_EN_DET_TEST_I, 0x00 },
	{ WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
	{ WSA881X_SPKR_DRV_EN, 0x74 },
	{ WSA881X_SPKR_DRV_DBG, 0x15 },
	{ WSA881X_SPKR_PWRSTG_DBG, 0x00 },
	{ WSA881X_SPKR_OCP_CTL, 0xD4 },
	{ WSA881X_SPKR_CLIP_CTL, 0x90 },
	{ WSA881X_SPKR_PA_INT, 0x54 },
	{ WSA881X_SPKR_BIAS_CAL, 0xAC },
	{ WSA881X_SPKR_STATUS1, 0x00 },
	{ WSA881X_SPKR_STATUS2, 0x00 },
	{ WSA881X_BOOST_EN_CTL, 0x18 },
	{ WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
	{ WSA881X_BOOST_PRESET_OUT2, 0x70 },
	{ WSA881X_BOOST_FORCE_OUT, 0x0E },
	{ WSA881X_BOOST_LDO_PROG, 0x16 },
	{ WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
	{ WSA881X_BOOST_RON_CTL, 0x0F },
	{ WSA881X_BOOST_ZX_CTL, 0x34 },
	{ WSA881X_BOOST_START_CTL, 0x23 },
	{ WSA881X_BOOST_MISC1_CTL, 0x80 },
	{ WSA881X_BOOST_MISC2_CTL, 0x00 },
	{ WSA881X_BOOST_MISC3_CTL, 0x00 },
	{ WSA881X_BOOST_ATEST_CTL, 0x00 },
	{ WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
	{ WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
	{ WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
	{ WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
	{ WSA881X_SPKR_PROT_ATEST1, 0x01 },
	{ WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
	{ WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
	{ WSA881X_SPKR_PROT_SAR, 0x00 },
	{ WSA881X_SPKR_STATUS3, 0x00 },
};

static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
	{ WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
	{ WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
};

static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
	{ WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
	{ WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
	{ WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
};

/* Default register reset values for WSA881x rev 2.0 */
static struct reg_sequence wsa881x_rev_2_0[] = {
	{ WSA881X_RESET_CTL, 0x00, 0x00 },
	{ WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
	{ WSA881X_INTR_MASK, 0x1B, 0x00 },
	{ WSA881X_IOPAD_CTL, 0x00, 0x00 },
	{ WSA881X_OTP_REG_28, 0x3F, 0x00 },
	{ WSA881X_OTP_REG_29, 0x3F, 0x00 },
	{ WSA881X_OTP_REG_30, 0x01, 0x00 },
	{ WSA881X_OTP_REG_31, 0x01, 0x00 },
	{ WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
	{ WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
	{ WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
	{ WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
	{ WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
	{ WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
	{ WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
	{ WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
	{ WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
	{ WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
	{ WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
	{ WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
	{ WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
	{ WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
	{ WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
};

enum wsa_port_ids {
	WSA881X_PORT_DAC,
	WSA881X_PORT_COMP,
	WSA881X_PORT_BOOST,
	WSA881X_PORT_VISENSE,
};

/* 4 ports */
static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
	{
		/* DAC */
		.num = 1,
		.type = SDW_DPN_SIMPLE,
		.min_ch = 1,
		.max_ch = 1,
		.simple_ch_prep_sm = true,
	}, {
		/* COMP */
		.num = 2,
		.type = SDW_DPN_SIMPLE,
		.min_ch = 1,
		.max_ch = 1,
		.simple_ch_prep_sm = true,
	}, {
		/* BOOST */
		.num = 3,
		.type = SDW_DPN_SIMPLE,
		.min_ch = 1,
		.max_ch = 1,
		.simple_ch_prep_sm = true,
	}, {
		/* VISENSE */
		.num = 4,
		.type = SDW_DPN_SIMPLE,
		.min_ch = 1,
		.max_ch = 1,
		.simple_ch_prep_sm = true,
	}
};

static struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
	{
		.num = 1,
		.ch_mask = 0x1,
	}, {
		.num = 2,
		.ch_mask = 0xf,
	}, {
		.num = 3,
		.ch_mask = 0x3,
	}, {	/* IV feedback */
		.num = 4,
		.ch_mask = 0x3,
	},
};

static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case WSA881X_CHIP_ID0:
	case WSA881X_CHIP_ID1:
	case WSA881X_CHIP_ID2:
	case WSA881X_CHIP_ID3:
	case WSA881X_BUS_ID:
	case WSA881X_CDC_RST_CTL:
	case WSA881X_CDC_TOP_CLK_CTL:
	case WSA881X_CDC_ANA_CLK_CTL:
	case WSA881X_CDC_DIG_CLK_CTL:
	case WSA881X_CLOCK_CONFIG:
	case WSA881X_ANA_CTL:
	case WSA881X_SWR_RESET_EN:
	case WSA881X_RESET_CTL:
	case WSA881X_TADC_VALUE_CTL:
	case WSA881X_TEMP_DETECT_CTL:
	case WSA881X_TEMP_MSB:
	case WSA881X_TEMP_LSB:
	case WSA881X_TEMP_CONFIG0:
	case WSA881X_TEMP_CONFIG1:
	case WSA881X_CDC_CLIP_CTL:
	case WSA881X_SDM_PDM9_LSB:
	case WSA881X_SDM_PDM9_MSB:
	case WSA881X_CDC_RX_CTL:
	case WSA881X_DEM_BYPASS_DATA0:
	case WSA881X_DEM_BYPASS_DATA1:
	case WSA881X_DEM_BYPASS_DATA2:
	case WSA881X_DEM_BYPASS_DATA3:
	case WSA881X_OTP_CTRL0:
	case WSA881X_OTP_CTRL1:
	case WSA881X_HDRIVE_CTL_GROUP1:
	case WSA881X_INTR_MODE:
	case WSA881X_INTR_MASK:
	case WSA881X_INTR_STATUS:
	case WSA881X_INTR_CLEAR:
	case WSA881X_INTR_LEVEL:
	case WSA881X_INTR_SET:
	case WSA881X_INTR_TEST:
	case WSA881X_PDM_TEST_MODE:
	case WSA881X_ATE_TEST_MODE:
	case WSA881X_PIN_CTL_MODE:
	case WSA881X_PIN_CTL_OE:
	case WSA881X_PIN_WDATA_IOPAD:
	case WSA881X_PIN_STATUS:
	case WSA881X_DIG_DEBUG_MODE:
	case WSA881X_DIG_DEBUG_SEL:
	case WSA881X_DIG_DEBUG_EN:
	case WSA881X_SWR_HM_TEST1:
	case WSA881X_SWR_HM_TEST2:
	case WSA881X_TEMP_DETECT_DBG_CTL:
	case WSA881X_TEMP_DEBUG_MSB:
	case WSA881X_TEMP_DEBUG_LSB:
	case WSA881X_SAMPLE_EDGE_SEL:
	case WSA881X_IOPAD_CTL:
	case WSA881X_SPARE_0:
	case WSA881X_SPARE_1:
	case WSA881X_SPARE_2:
	case WSA881X_OTP_REG_0:
	case WSA881X_OTP_REG_1:
	case WSA881X_OTP_REG_2:
	case WSA881X_OTP_REG_3:
	case WSA881X_OTP_REG_4:
	case WSA881X_OTP_REG_5:
	case WSA881X_OTP_REG_6:
	case WSA881X_OTP_REG_7:
	case WSA881X_OTP_REG_8:
	case WSA881X_OTP_REG_9:
	case WSA881X_OTP_REG_10:
	case WSA881X_OTP_REG_11:
	case WSA881X_OTP_REG_12:
	case WSA881X_OTP_REG_13:
	case WSA881X_OTP_REG_14:
	case WSA881X_OTP_REG_15:
	case WSA881X_OTP_REG_16:
	case WSA881X_OTP_REG_17:
	case WSA881X_OTP_REG_18:
	case WSA881X_OTP_REG_19:
	case WSA881X_OTP_REG_20:
	case WSA881X_OTP_REG_21:
	case WSA881X_OTP_REG_22:
	case WSA881X_OTP_REG_23:
	case WSA881X_OTP_REG_24:
	case WSA881X_OTP_REG_25:
	case WSA881X_OTP_REG_26:
	case WSA881X_OTP_REG_27:
	case WSA881X_OTP_REG_28:
	case WSA881X_OTP_REG_29:
	case WSA881X_OTP_REG_30:
	case WSA881X_OTP_REG_31:
	case WSA881X_OTP_REG_63:
	case WSA881X_BIAS_REF_CTRL:
	case WSA881X_BIAS_TEST:
	case WSA881X_BIAS_BIAS:
	case WSA881X_TEMP_OP:
	case WSA881X_TEMP_IREF_CTRL:
	case WSA881X_TEMP_ISENS_CTRL:
	case WSA881X_TEMP_CLK_CTRL:
	case WSA881X_TEMP_TEST:
	case WSA881X_TEMP_BIAS:
	case WSA881X_TEMP_ADC_CTRL:
	case WSA881X_TEMP_DOUT_MSB:
	case WSA881X_TEMP_DOUT_LSB:
	case WSA881X_ADC_EN_MODU_V:
	case WSA881X_ADC_EN_MODU_I:
	case WSA881X_ADC_EN_DET_TEST_V:
	case WSA881X_ADC_EN_DET_TEST_I:
	case WSA881X_ADC_SEL_IBIAS:
	case WSA881X_ADC_EN_SEL_IBAIS:
	case WSA881X_SPKR_DRV_EN:
	case WSA881X_SPKR_DRV_GAIN:
	case WSA881X_SPKR_DAC_CTL:
	case WSA881X_SPKR_DRV_DBG:
	case WSA881X_SPKR_PWRSTG_DBG:
	case WSA881X_SPKR_OCP_CTL:
	case WSA881X_SPKR_CLIP_CTL:
	case WSA881X_SPKR_BBM_CTL:
	case WSA881X_SPKR_MISC_CTL1:
	case WSA881X_SPKR_MISC_CTL2:
	case WSA881X_SPKR_BIAS_INT:
	case WSA881X_SPKR_PA_INT:
	case WSA881X_SPKR_BIAS_CAL:
	case WSA881X_SPKR_BIAS_PSRR:
	case WSA881X_SPKR_STATUS1:
	case WSA881X_SPKR_STATUS2:
	case WSA881X_BOOST_EN_CTL:
	case WSA881X_BOOST_CURRENT_LIMIT:
	case WSA881X_BOOST_PS_CTL:
	case WSA881X_BOOST_PRESET_OUT1:
	case WSA881X_BOOST_PRESET_OUT2:
	case WSA881X_BOOST_FORCE_OUT:
	case WSA881X_BOOST_LDO_PROG:
	case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
	case WSA881X_BOOST_RON_CTL:
	case WSA881X_BOOST_LOOP_STABILITY:
	case WSA881X_BOOST_ZX_CTL:
	case WSA881X_BOOST_START_CTL:
	case WSA881X_BOOST_MISC1_CTL:
	case WSA881X_BOOST_MISC2_CTL:
	case WSA881X_BOOST_MISC3_CTL:
	case WSA881X_BOOST_ATEST_CTL:
	case WSA881X_SPKR_PROT_FE_GAIN:
	case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
	case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
	case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
	case WSA881X_SPKR_PROT_ATEST1:
	case WSA881X_SPKR_PROT_ATEST2:
	case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
	case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
	case WSA881X_BONGO_RESRV_REG1:
	case WSA881X_BONGO_RESRV_REG2:
	case WSA881X_SPKR_PROT_SAR:
	case WSA881X_SPKR_STATUS3:
		return true;
	default:
		return false;
	}
}

static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case WSA881X_CHIP_ID0:
	case WSA881X_CHIP_ID1:
	case WSA881X_CHIP_ID2:
	case WSA881X_CHIP_ID3:
	case WSA881X_BUS_ID:
	case WSA881X_TEMP_MSB:
	case WSA881X_TEMP_LSB:
	case WSA881X_SDM_PDM9_LSB:
	case WSA881X_SDM_PDM9_MSB:
	case WSA881X_OTP_CTRL1:
	case WSA881X_INTR_STATUS:
	case WSA881X_ATE_TEST_MODE:
	case WSA881X_PIN_STATUS:
	case WSA881X_SWR_HM_TEST2:
	case WSA881X_SPKR_STATUS1:
	case WSA881X_SPKR_STATUS2:
	case WSA881X_SPKR_STATUS3:
	case WSA881X_OTP_REG_0:
	case WSA881X_OTP_REG_1:
	case WSA881X_OTP_REG_2:
	case WSA881X_OTP_REG_3:
	case WSA881X_OTP_REG_4:
	case WSA881X_OTP_REG_5:
	case WSA881X_OTP_REG_31:
	case WSA881X_TEMP_DOUT_MSB:
	case WSA881X_TEMP_DOUT_LSB:
	case WSA881X_TEMP_OP:
	case WSA881X_SPKR_PROT_SAR:
		return true;
	default:
		return false;
	}
}

static struct regmap_config wsa881x_regmap_config = {
	.reg_bits = 32,
	.val_bits = 8,
	.cache_type = REGCACHE_RBTREE,
	.reg_defaults = wsa881x_defaults,
	.num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
	.volatile_reg = wsa881x_volatile_register,
	.readable_reg = wsa881x_readable_register,
	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
	.val_format_endian = REGMAP_ENDIAN_NATIVE,
	.can_multi_write = true,
};

enum {
	G_18DB = 0,
	G_16P5DB,
	G_15DB,
	G_13P5DB,
	G_12DB,
	G_10P5DB,
	G_9DB,
	G_7P5DB,
	G_6DB,
	G_4P5DB,
	G_3DB,
	G_1P5DB,
	G_0DB,
};

/*
 * Private data Structure for wsa881x. All parameters related to
 * WSA881X codec needs to be defined here.
 */
struct wsa881x_priv {
	struct regmap *regmap;
	struct device *dev;
	struct sdw_slave *slave;
	struct sdw_stream_config sconfig;
	struct sdw_stream_runtime *sruntime;
	struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
	struct gpio_desc *sd_n;
	int version;
	int active_ports;
	bool port_prepared[WSA881X_MAX_SWR_PORTS];
	bool port_enable[WSA881X_MAX_SWR_PORTS];
	bool stream_prepared;
};

static void wsa881x_init(struct wsa881x_priv *wsa881x)
{
	struct regmap *rm = wsa881x->regmap;
	unsigned int val = 0;

	regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version);
	regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
			      ARRAY_SIZE(wsa881x_rev_2_0));

	/* Enable software reset output from soundwire slave */
	regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);

	/* Bring out of analog reset */
	regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);

	/* Bring out of digital reset */
	regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
	regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
	regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
	regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
	regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
	regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
	regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
	regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
	regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
	regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
	regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
	regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
	regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
	regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);

	regmap_read(rm, WSA881X_OTP_REG_0, &val);
	if (val)
		regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);

	regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
	regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
	regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
	regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
	regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
	regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
	regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
	regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
}

static int wsa881x_component_probe(struct snd_soc_component *comp)
{
	struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);

	snd_soc_component_init_regmap(comp, wsa881x->regmap);

	return 0;
}

static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
			       struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
	struct soc_mixer_control *mc =
			(struct soc_mixer_control *)kc->private_value;
	int max = mc->max;
	unsigned int mask = (1 << fls(max)) - 1;
	int val, ret, min_gain, max_gain;

	max_gain = (max - ucontrol->value.integer.value[0]) & mask;
	/*
	 * Gain has to set incrementally in 4 steps
	 * as per HW sequence
	 */
	if (max_gain > G_4P5DB)
		min_gain = G_0DB;
	else
		min_gain = max_gain + 3;
	/*
	 * 1ms delay is needed before change in gain
	 * as per HW requirement.
	 */
	usleep_range(1000, 1010);

	for (val = min_gain; max_gain <= val; val--) {
		ret = snd_soc_component_update_bits(comp,
			      WSA881X_SPKR_DRV_GAIN,
			      WSA881X_SPKR_PAG_GAIN_MASK,
			      val << 4);
		if (ret < 0)
			dev_err(comp->dev, "Failed to change PA gain");

		usleep_range(1000, 1010);
	}
	return 0;
}

static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
			    struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
	struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
	struct soc_mixer_control *mixer =
		(struct soc_mixer_control *)kcontrol->private_value;
	int portidx = mixer->reg;

	ucontrol->value.integer.value[0] = data->port_enable[portidx];


	return 0;
}

static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
{
	if (enable)
		snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
					      WSA881X_BOOST_EN_MASK,
					      WSA881X_BOOST_EN);
	else
		snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
					      WSA881X_BOOST_EN_MASK, 0);
	/*
	 * 1.5ms sleep is needed after boost enable/disable as per
	 * HW requirement
	 */
	usleep_range(1500, 1510);
	return 0;
}

static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
			    struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
	struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
	struct soc_mixer_control *mixer =
		(struct soc_mixer_control *)kcontrol->private_value;
	int portidx = mixer->reg;

	if (ucontrol->value.integer.value[0])
		data->port_enable[portidx] = true;
	else
		data->port_enable[portidx] = false;

	if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
		wsa881x_boost_ctrl(comp, data->port_enable[portidx]);

	return 0;
}

static const char * const smart_boost_lvl_text[] = {
	"6.625 V", "6.750 V", "6.875 V", "7.000 V",
	"7.125 V", "7.250 V", "7.375 V", "7.500 V",
	"7.625 V", "7.750 V", "7.875 V", "8.000 V",
	"8.125 V", "8.250 V", "8.375 V", "8.500 V"
};

static const struct soc_enum smart_boost_lvl_enum =
	SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
			ARRAY_SIZE(smart_boost_lvl_text),
			smart_boost_lvl_text);

static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);

static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
	SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
	WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
			    4, 0xC, 1, pa_gain),
	SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
		       wsa881x_get_port, wsa881x_set_port),
	SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
		       wsa881x_get_port, wsa881x_set_port),
	SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
		       wsa881x_get_port, wsa881x_set_port),
	SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
		       wsa881x_get_port, wsa881x_set_port),
};

static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
	{ "RDAC", NULL, "IN" },
	{ "RDAC", NULL, "DCLK" },
	{ "RDAC", NULL, "ACLK" },
	{ "RDAC", NULL, "Bandgap" },
	{ "SPKR PGA", NULL, "RDAC" },
	{ "SPKR", NULL, "SPKR PGA" },
};

static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
				     bool enable)
{
	struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);

	if (enable) {
		regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
				       ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
	} else {
		snd_soc_component_update_bits(comp,
					      WSA881X_SPKR_PROT_FE_VSENSE_VCM,
					      0x08, 0x08);
		/*
		 * 200us sleep is needed after visense txfe disable as per
		 * HW requirement.
		 */
		usleep_range(200, 210);
		snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
					      0x01, 0x00);
	}
	return 0;
}

static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
				    bool enable)
{
	snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
				      (enable << 7));
	snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
				      (enable << 7));
	return 0;
}

static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
				 struct snd_kcontrol *kcontrol, int event)
{
	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
	struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
					      WSA881X_SPKR_OCP_MASK,
					      WSA881X_SPKR_OCP_EN);
		regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
				       ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));

		snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
					      WSA881X_PA_GAIN_SEL_MASK,
					      WSA881X_PA_GAIN_SEL_REG);
		break;
	case SND_SOC_DAPM_POST_PMU:
		if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
			wsa881x_visense_txfe_ctrl(comp, true);
			snd_soc_component_update_bits(comp,
						      WSA881X_ADC_EN_SEL_IBAIS,
						      0x07, 0x01);
			wsa881x_visense_adc_ctrl(comp, true);
		}

		break;
	case SND_SOC_DAPM_POST_PMD:
		if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
			wsa881x_visense_adc_ctrl(comp, false);
			wsa881x_visense_txfe_ctrl(comp, false);
		}

		snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
					      WSA881X_SPKR_OCP_MASK,
					      WSA881X_SPKR_OCP_EN |
					      WSA881X_SPKR_OCP_HOLD);
		break;
	}
	return 0;
}

static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
	SND_SOC_DAPM_INPUT("IN"),
	SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
			   NULL,
			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
			   wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
			   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
			    NULL,
			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_OUTPUT("SPKR"),
};

static int wsa881x_prepare(struct snd_pcm_substream *substream,
			   struct snd_soc_dai *dai)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
	int ret;

	if (wsa881x->stream_prepared) {
		sdw_disable_stream(wsa881x->sruntime);
		sdw_deprepare_stream(wsa881x->sruntime);
		wsa881x->stream_prepared = false;
	}


	ret = sdw_prepare_stream(wsa881x->sruntime);
	if (ret)
		return ret;

	/**
	 * NOTE: there is a strict hw requirement about the ordering of port
	 * enables and actual PA enable. PA enable should only happen after
	 * soundwire ports are enabled if not DC on the line is accumulated
	 * resulting in Click/Pop Noise
	 * PA enable/mute are handled as part of DAPM and digital mute.
	 */

	ret = sdw_enable_stream(wsa881x->sruntime);
	if (ret) {
		sdw_deprepare_stream(wsa881x->sruntime);
		return ret;
	}
	wsa881x->stream_prepared = true;

	return ret;
}

static int wsa881x_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *params,
			     struct snd_soc_dai *dai)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
	int i;

	wsa881x->active_ports = 0;
	for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
		if (!wsa881x->port_enable[i])
			continue;

		wsa881x->port_config[wsa881x->active_ports] =
							wsa881x_pconfig[i];
		wsa881x->active_ports++;
	}

	return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
				    wsa881x->port_config, wsa881x->active_ports,
				    wsa881x->sruntime);
}

static int wsa881x_hw_free(struct snd_pcm_substream *substream,
			   struct snd_soc_dai *dai)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);

	if (wsa881x->stream_prepared) {
		sdw_disable_stream(wsa881x->sruntime);
		sdw_deprepare_stream(wsa881x->sruntime);
		sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
		wsa881x->stream_prepared = false;
	}

	return 0;
}

static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
				  void *stream, int direction)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);

	wsa881x->sruntime = stream;

	return 0;
}

static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);

	if (mute)
		regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
				   0x00);
	else
		regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
				   0x80);

	return 0;
}

static struct snd_soc_dai_ops wsa881x_dai_ops = {
	.hw_params = wsa881x_hw_params,
	.prepare = wsa881x_prepare,
	.hw_free = wsa881x_hw_free,
	.mute_stream = wsa881x_digital_mute,
	.set_sdw_stream = wsa881x_set_sdw_stream,
};

static struct snd_soc_dai_driver wsa881x_dais[] = {
	{
		.name = "SPKR",
		.id = 0,
		.playback = {
			.stream_name = "SPKR Playback",
			.rate_max = 48000,
			.rate_min = 48000,
			.channels_min = 1,
			.channels_max = 1,
		},
		.ops = &wsa881x_dai_ops,
	},
};

static const struct snd_soc_component_driver wsa881x_component_drv = {
	.name = "WSA881x",
	.probe = wsa881x_component_probe,
	.controls = wsa881x_snd_controls,
	.num_controls = ARRAY_SIZE(wsa881x_snd_controls),
	.dapm_widgets = wsa881x_dapm_widgets,
	.num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
	.dapm_routes = wsa881x_audio_map,
	.num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
};

static int wsa881x_update_status(struct sdw_slave *slave,
				 enum sdw_slave_status status)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);

	if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
		wsa881x_init(wsa881x);

	return 0;
}

static int wsa881x_port_prep(struct sdw_slave *slave,
			     struct sdw_prepare_ch *prepare_ch,
			     enum sdw_port_prep_ops state)
{
	struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);

	if (state == SDW_OPS_PORT_POST_PREP)
		wsa881x->port_prepared[prepare_ch->num - 1] = true;
	else
		wsa881x->port_prepared[prepare_ch->num - 1] = false;

	return 0;
}

static int wsa881x_bus_config(struct sdw_slave *slave,
			      struct sdw_bus_params *params)
{
	sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
		  0x01);

	return 0;
}

static struct sdw_slave_ops wsa881x_slave_ops = {
	.update_status = wsa881x_update_status,
	.bus_config = wsa881x_bus_config,
	.port_prep = wsa881x_port_prep,
};

static int wsa881x_probe(struct sdw_slave *pdev,
			 const struct sdw_device_id *id)
{
	struct wsa881x_priv *wsa881x;

	wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
	if (!wsa881x)
		return -ENOMEM;

	wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
						GPIOD_FLAGS_BIT_NONEXCLUSIVE);
	if (IS_ERR(wsa881x->sd_n)) {
		dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
		return PTR_ERR(wsa881x->sd_n);
	}

	dev_set_drvdata(&pdev->dev, wsa881x);
	wsa881x->slave = pdev;
	wsa881x->dev = &pdev->dev;
	wsa881x->sconfig.ch_count = 1;
	wsa881x->sconfig.bps = 1;
	wsa881x->sconfig.frame_rate = 48000;
	wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
	wsa881x->sconfig.type = SDW_STREAM_PDM;
	pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
	pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
	gpiod_set_value(wsa881x->sd_n, 1);

	wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
	if (IS_ERR(wsa881x->regmap)) {
		dev_err(&pdev->dev, "regmap_init failed\n");
		return PTR_ERR(wsa881x->regmap);
	}

	return devm_snd_soc_register_component(&pdev->dev,
					       &wsa881x_component_drv,
					       wsa881x_dais,
					       ARRAY_SIZE(wsa881x_dais));
}

static const struct sdw_device_id wsa881x_slave_id[] = {
	SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
	SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
	{},
};
MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);

static struct sdw_driver wsa881x_codec_driver = {
	.probe	= wsa881x_probe,
	.ops = &wsa881x_slave_ops,
	.id_table = wsa881x_slave_id,
	.driver = {
		.name	= "wsa881x-codec",
	}
};
module_sdw_driver(wsa881x_codec_driver);

MODULE_DESCRIPTION("WSA881x codec driver");
MODULE_LICENSE("GPL v2");