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/*
* OMAP4 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo (t-kristo@ti.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include "clock.h"
/*
* OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
* "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
* must be set to 196.608 MHz" and hence, the DPLL locked frequency is
* half of this value.
*/
#define OMAP4_DPLL_ABE_DEFFREQ 98304000
/*
* OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
* "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
* locked frequency for the USB DPLL is 960MHz.
*/
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK("smp_twd", NULL, "mpu_periphclk"),
DT_CLK("omapdss_dss", "ick", "dss_fck"),
DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
DT_CLK(NULL, "uart1_ick", "dummy_ck"),
DT_CLK(NULL, "uart2_ick", "dummy_ck"),
DT_CLK(NULL, "uart3_ick", "dummy_ck"),
DT_CLK(NULL, "uart4_ick", "dummy_ck"),
DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
{ .node_name = NULL },
};
int __init omap4xxx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
ti_dt_clocks_register(omap44xx_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
/*
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
/*
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
* state when turning the ABE clock domain. Workaround this by
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
return 0;
}
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