summaryrefslogtreecommitdiffstats
path: root/drivers/clk/clk-qoriq.c
blob: 90ff6858c900a07767d99b2b1678f0d7fa72c413 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * clock driver for Freescale QorIQ SoCs.
 */
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of.h>
#include <linux/slab.h>

struct cmux_clk {
	struct clk_hw hw;
	void __iomem *reg;
	unsigned int clk_per_pll;
	u32 flags;
};

#define PLL_KILL			BIT(31)
#define	CLKSEL_SHIFT		27
#define CLKSEL_ADJUST		BIT(0)
#define to_cmux_clk(p)		container_of(p, struct cmux_clk, hw)

static int cmux_set_parent(struct clk_hw *hw, u8 idx)
{
	struct cmux_clk *clk = to_cmux_clk(hw);
	u32 clksel;

	clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll;
	if (clk->flags & CLKSEL_ADJUST)
		clksel += 8;
	clksel = (clksel & 0xf) << CLKSEL_SHIFT;
	iowrite32be(clksel, clk->reg);

	return 0;
}

static u8 cmux_get_parent(struct clk_hw *hw)
{
	struct cmux_clk *clk = to_cmux_clk(hw);
	u32 clksel;

	clksel = ioread32be(clk->reg);
	clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
	if (clk->flags & CLKSEL_ADJUST)
		clksel -= 8;
	clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4;

	return clksel;
}

const struct clk_ops cmux_ops = {
	.get_parent = cmux_get_parent,
	.set_parent = cmux_set_parent,
};

static void __init core_mux_init(struct device_node *np)
{
	struct clk *clk;
	struct clk_init_data init;
	struct cmux_clk *cmux_clk;
	struct device_node *node;
	int rc, count, i;
	u32	offset;
	const char *clk_name;
	const char **parent_names;
	struct of_phandle_args clkspec;

	rc = of_property_read_u32(np, "reg", &offset);
	if (rc) {
		pr_err("%s: could not get reg property\n", np->name);
		return;
	}

	/* get the input clock source count */
	count = of_property_count_strings(np, "clock-names");
	if (count < 0) {
		pr_err("%s: get clock count error\n", np->name);
		return;
	}
	parent_names = kzalloc((sizeof(char *) * count), GFP_KERNEL);
	if (!parent_names) {
		pr_err("%s: could not allocate parent_names\n", __func__);
		return;
	}

	for (i = 0; i < count; i++)
		parent_names[i] = of_clk_get_parent_name(np, i);

	cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);
	if (!cmux_clk) {
		pr_err("%s: could not allocate cmux_clk\n", __func__);
		goto err_name;
	}
	cmux_clk->reg = of_iomap(np, 0);
	if (!cmux_clk->reg) {
		pr_err("%s: could not map register\n", __func__);
		goto err_clk;
	}

	rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
					&clkspec);
	if (rc) {
		pr_err("%s: parse clock node error\n", __func__);
		goto err_clk;
	}

	cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,
			"clock-output-names");
	of_node_put(clkspec.np);

	node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
	if (node && (offset >= 0x80))
		cmux_clk->flags = CLKSEL_ADJUST;

	rc = of_property_read_string_index(np, "clock-output-names",
					   0, &clk_name);
	if (rc) {
		pr_err("%s: read clock names error\n", np->name);
		goto err_clk;
	}

	init.name = clk_name;
	init.ops = &cmux_ops;
	init.parent_names = parent_names;
	init.num_parents = count;
	init.flags = 0;
	cmux_clk->hw.init = &init;

	clk = clk_register(NULL, &cmux_clk->hw);
	if (IS_ERR(clk)) {
		pr_err("%s: could not register clock\n", clk_name);
		goto err_clk;
	}

	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
	if (rc) {
		pr_err("Could not register clock provider for node:%s\n",
		       np->name);
		goto err_clk;
	}
	goto err_name;

err_clk:
	kfree(cmux_clk);
err_name:
	/* free *_names because they are reallocated when registered */
	kfree(parent_names);
}

static void __init core_pll_init(struct device_node *np)
{
	u32 mult;
	int i, rc, count;
	const char *clk_name, *parent_name;
	struct clk_onecell_data *onecell_data;
	struct clk      **subclks;
	void __iomem *base;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("clk-qoriq: iomap error\n");
		return;
	}

	/* get the multiple of PLL */
	mult = ioread32be(base);

	/* check if this PLL is disabled */
	if (mult & PLL_KILL) {
		pr_debug("PLL:%s is disabled\n", np->name);
		goto err_map;
	}
	mult = (mult >> 1) & 0x3f;

	parent_name = of_clk_get_parent_name(np, 0);
	if (!parent_name) {
		pr_err("PLL: %s must have a parent\n", np->name);
		goto err_map;
	}

	count = of_property_count_strings(np, "clock-output-names");
	if (count < 0 || count > 4) {
		pr_err("%s: clock is not supported\n", np->name);
		goto err_map;
	}

	subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
	if (!subclks) {
		pr_err("%s: could not allocate subclks\n", __func__);
		goto err_map;
	}

	onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
	if (!onecell_data) {
		pr_err("%s: could not allocate onecell_data\n", __func__);
		goto err_clks;
	}

	for (i = 0; i < count; i++) {
		rc = of_property_read_string_index(np, "clock-output-names",
						   i, &clk_name);
		if (rc) {
			pr_err("%s: could not get clock names\n", np->name);
			goto err_cell;
		}

		/*
		 * when count == 4, there are 4 output clocks:
		 * /1, /2, /3, /4 respectively
		 * when count < 4, there are at least 2 output clocks:
		 * /1, /2, (/4, if count == 3) respectively.
		 */
		if (count == 4)
			subclks[i] = clk_register_fixed_factor(NULL, clk_name,
					parent_name, 0, mult, 1 + i);
		else

			subclks[i] = clk_register_fixed_factor(NULL, clk_name,
					parent_name, 0, mult, 1 << i);

		if (IS_ERR(subclks[i])) {
			pr_err("%s: could not register clock\n", clk_name);
			goto err_cell;
		}
	}

	onecell_data->clks = subclks;
	onecell_data->clk_num = count;

	rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
	if (rc) {
		pr_err("Could not register clk provider for node:%s\n",
		       np->name);
		goto err_cell;
	}

	iounmap(base);
	return;
err_cell:
	kfree(onecell_data);
err_clks:
	kfree(subclks);
err_map:
	iounmap(base);
}

static void __init sysclk_init(struct device_node *node)
{
	struct clk *clk;
	const char *clk_name = node->name;
	struct device_node *np = of_get_parent(node);
	u32 rate;

	if (!np) {
		pr_err("qoriq-clk: could not get parent node\n");
		return;
	}

	if (of_property_read_u32(np, "clock-frequency", &rate)) {
		of_node_put(node);
		return;
	}

	of_property_read_string(np, "clock-output-names", &clk_name);

	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
	if (!IS_ERR(clk))
		of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);