summaryrefslogtreecommitdiffstats
path: root/arch/mn10300/mm/cache-flush-by-reg.S
blob: 1dcae0211671db7362bd7bd85aa62961039f1f2d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
/* MN10300 CPU core caching routines, using indirect regs on cache controller
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */

#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/smp.h>
#include <asm/page.h>
#include <asm/cache.h>
#include <asm/irqflags.h>

	.am33_2

#ifndef CONFIG_SMP
	.globl mn10300_dcache_flush
	.globl mn10300_dcache_flush_page
	.globl mn10300_dcache_flush_range
	.globl mn10300_dcache_flush_range2
	.globl mn10300_dcache_flush_inv
	.globl mn10300_dcache_flush_inv_page
	.globl mn10300_dcache_flush_inv_range
	.globl mn10300_dcache_flush_inv_range2

mn10300_dcache_flush		= mn10300_local_dcache_flush
mn10300_dcache_flush_page	= mn10300_local_dcache_flush_page
mn10300_dcache_flush_range	= mn10300_local_dcache_flush_range
mn10300_dcache_flush_range2	= mn10300_local_dcache_flush_range2
mn10300_dcache_flush_inv	= mn10300_local_dcache_flush_inv
mn10300_dcache_flush_inv_page	= mn10300_local_dcache_flush_inv_page
mn10300_dcache_flush_inv_range	= mn10300_local_dcache_flush_inv_range
mn10300_dcache_flush_inv_range2	= mn10300_local_dcache_flush_inv_range2

#endif /* !CONFIG_SMP */

###############################################################################
#
# void mn10300_local_dcache_flush(void)
# Flush the entire data cache back to RAM
#
###############################################################################
	ALIGN
	.globl	mn10300_local_dcache_flush
        .type	mn10300_local_dcache_flush,@function
mn10300_local_dcache_flush:
	movhu	(CHCTR),d0
	btst	CHCTR_DCEN,d0
	beq	mn10300_local_dcache_flush_end

	mov	DCPGCR,a0

	LOCAL_CLI_SAVE(d1)

	# wait for busy bit of area purge
	setlb
	mov	(a0),d0
	btst	DCPGCR_DCPGBSY,d0
	lne

	# set mask
	clr	d0
	mov	d0,(DCPGMR)

	# area purge
	#
	# DCPGCR = DCPGCR_DCP
	#
	mov	DCPGCR_DCP,d0
	mov	d0,(a0)

	# wait for busy bit of area purge
	setlb
	mov	(a0),d0
	btst	DCPGCR_DCPGBSY,d0
	lne

	LOCAL_IRQ_RESTORE(d1)

mn10300_local_dcache_flush_end:
	ret	[],0
	.size	mn10300_local_dcache_flush,.-mn10300_local_dcache_flush

###############################################################################
#
# void mn10300_local_dcache_flush_page(unsigned long start)
# void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end)
# void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size)
# Flush a range of addresses on a page in the dcache
#
###############################################################################
	ALIGN
	.globl	mn10300_local_dcache_flush_page
	.globl	mn10300_local_dcache_flush_range
	.globl	mn10300_local_dcache_flush_range2
	.type	mn10300_local_dcache_flush_page,@function
	.type	mn10300_local_dcache_flush_range,@function
	.type	mn10300_local_dcache_flush_range2,@function
mn10300_local_dcache_flush_page:
	and	~(PAGE_SIZE-1),d0
	mov	PAGE_SIZE,d1
mn10300_local_dcache_flush_range2:
	add	d0,d1
mn10300_local_dcache_flush_range:
	movm	[d2,d3,a2],(sp)

	movhu	(CHCTR),d2
	btst	CHCTR_DCEN,d2
	beq	mn10300_local_dcache_flush_range_end

	# calculate alignsize
	#
	# alignsize = L1_CACHE_BYTES;
	# for (i = (end - start - 1) / L1_CACHE_BYTES ;  i > 0; i >>= 1)
	#     alignsize <<= 1;
	# d2 = alignsize;
	#
	mov	L1_CACHE_BYTES,d2
	sub	d0,d1,d3
	add	-1,d3
	lsr	L1_CACHE_SHIFT,d3
	beq	2f
1:
	add     d2,d2
	lsr     1,d3
	bne     1b
2:
	mov	d1,a1		# a1 = end

	LOCAL_CLI_SAVE(d3)
	mov	DCPGCR,a0

	# wait for busy bit of area purge
	setlb
	mov	(a0),d1
	btst	DCPGCR_DCPGBSY,d1
	lne

	# determine the mask
	mov	d2,d1
	add	-1,d1
	not	d1		# d1 = mask = ~(alignsize-1)
	mov	d1,(DCPGMR)

	and	d1,d0,a2	# a2 = mask & start

dcpgloop:
	# area purge
	mov	a2,d0
	or	DCPGCR_DCP,d0
	mov	d0,(a0)		# DCPGCR = (mask & start) | DCPGCR_DCP

	# wait for busy bit of area purge
	setlb
	mov	(a0),d1
	btst	DCPGCR_DCPGBSY,d1
	lne

	# check purge of end address
	add	d2,a2		# a2 += alignsize
	cmp	a1,a2		# if (a2 < end) goto dcpgloop
	bns	dcpgloop

	LOCAL_IRQ_RESTORE(d3)

mn10300_local_dcache_flush_range_end:
	ret	[d2,d3,a2],12

	.size	mn10300_local_dcache_flush_page,.-mn10300_local_dcache_flush_page
	.size	mn10300_local_dcache_flush_range,.-mn10300_local_dcache_flush_range
	.size	mn10300_local_dcache_flush_range2,.-mn10300_local_dcache_flush_range2

###############################################################################
#
# void mn10300_local_dcache_flush_inv(void)
# Flush the entire data cache and invalidate all entries
#
###############################################################################
	ALIGN
	.globl	mn10300_local_dcache_flush_inv
	.type	mn10300_local_dcache_flush_inv,@function
mn10300_local_dcache_flush_inv:
	movhu	(CHCTR),d0
	btst	CHCTR_DCEN,d0
	beq	mn10300_local_dcache_flush_inv_end

	mov	DCPGCR,a0

	LOCAL_CLI_SAVE(d1)

	# wait for busy bit of area purge & invalidate
	setlb
	mov	(a0),d0
	btst	DCPGCR_DCPGBSY,d0
	lne

	# set the mask to cover everything
	clr	d0
	mov	d0,(DCPGMR)

	# area purge & invalidate
	mov	DCPGCR_DCP|DCPGCR_DCI,d0
	mov	d0,(a0)

	# wait for busy bit of area purge & invalidate
	setlb
	mov	(a0),d0
	btst	DCPGCR_DCPGBSY,d0
	lne

	LOCAL_IRQ_RESTORE(d1)

mn10300_local_dcache_flush_inv_end:
	ret	[],0
	.size	mn10300_local_dcache_flush_inv,.-mn10300_local_dcache_flush_inv

###############################################################################
#
# void mn10300_local_dcache_flush_inv_page(unsigned long start)
# void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end)
# void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size)
# Flush and invalidate a range of addresses on a page in the dcache
#
###############################################################################
	ALIGN
	.globl	mn10300_local_dcache_flush_inv_page
	.globl	mn10300_local_dcache_flush_inv_range
	.globl	mn10300_local_dcache_flush_inv_range2
	.type	mn10300_local_dcache_flush_inv_page,@function
	.type	mn10300_local_dcache_flush_inv_range,@function
	.type	mn10300_local_dcache_flush_inv_range2,@function
mn10300_local_dcache_flush_inv_page:
	and	~(PAGE_SIZE-1),d0
	mov	PAGE_SIZE,d1
mn10300_local_dcache_flush_inv_range2:
	add	d0,d1
mn10300_local_dcache_flush_inv_range:
	movm	[d2,d3,a2],(sp)

	movhu	(CHCTR),d2
	btst	CHCTR_DCEN,d2
	beq	mn10300_local_dcache_flush_inv_range_end

	# calculate alignsize
	#
	# alignsize = L1_CACHE_BYTES;
	# for (i = (end - start - 1) / L1_CACHE_BYTES; i > 0; i >>= 1)
	#     alignsize <<= 1;
	# d2 = alignsize
	#
	mov	L1_CACHE_BYTES,d2
	sub	d0,d1,d3
	add	-1,d3
	lsr	L1_CACHE_SHIFT,d3
	beq	2f
1:
	add     d2,d2
	lsr     1,d3
	bne     1b
2:
	mov	d1,a1		# a1 = end

	LOCAL_CLI_SAVE(d3)
	mov	DCPGCR,a0

	# wait for busy bit of area purge & invalidate
	setlb
	mov	(a0),d1
	btst	DCPGCR_DCPGBSY,d1
	lne

	# set the mask
	mov	d2,d1
	add	-1,d1
	not	d1		# d1 = mask = ~(alignsize-1)
	mov	d1,(DCPGMR)

	and	d1,d0,a2	# a2 = mask & start

dcpgivloop:
	# area purge & invalidate
	mov	a2,d0
	or	DCPGCR_DCP|DCPGCR_DCI,d0
	mov	d0,(a0)		# DCPGCR = (mask & start)|DCPGCR_DCP|DCPGCR_DCI

	# wait for busy bit of area purge & invalidate
	setlb
	mov	(a0),d1
	btst	DCPGCR_DCPGBSY,d1
	lne

	# check purge & invalidate of end address
	add	d2,a2		# a2 += alignsize
	cmp	a1,a2		# if (a2 < end) goto dcpgivloop
	bns	dcpgivloop

	LOCAL_IRQ_RESTORE(d3)

mn10300_local_dcache_flush_inv_range_end:
	ret	[d2,d3,a2],12
	.size	mn10300_local_dcache_flush_inv_page,.-mn10300_local_dcache_flush_inv_page
	.size	mn10300_local_dcache_flush_inv_range,.-mn10300_local_dcache_flush_inv_range
	.size	mn10300_local_dcache_flush_inv_range2,.-mn10300_local_dcache_flush_inv_range2