blob: bd85da3d6770adc9d55674f36b214b9124e534c2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
* Douglas Leung <douglas@mips.com>
* Steven J. Hill <sjhill@mips.com>
*/
#ifndef _MIPS_SEAD3INT_H
#define _MIPS_SEAD3INT_H
#include <linux/irqchip/mips-gic.h>
/* CPU interrupt offsets */
#define CPU_INT_EHCI 2
#define CPU_INT_UART0 4
#define CPU_INT_UART1 4
#define CPU_INT_NET 6
/* GIC interrupt offsets */
#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
#define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2)
#define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3)
#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
#endif /* !(_MIPS_SEAD3INT_H) */
|
