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/dts-v1/;
/ {
compatible = "gnu,gdbsim";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&h8intc>;
chosen {
bootargs = "earlyprintk=h8300-sim";
stdout-path = <&sci0>;
};
aliases {
serial0 = &sci0;
serial1 = &sci1;
};
xclk: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
clock-output-names = "xtal";
};
core_clk: core_clk {
compatible = "renesas,h8300-div-clock";
clocks = <&xclk>;
#clock-cells = <0>;
reg = <0xfee01b 2>;
renesas,width = <2>;
};
fclk: fclk {
compatible = "fixed-factor-clock";
clocks = <&core_clk>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
memory@400000 {
device_type = "memory";
reg = <0x400000 0x400000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "renesas,h8300";
clock-frequency = <20000000>;
};
};
h8intc: interrupt-controller@fee012 {
compatible = "renesas,h8300h-intc", "renesas,h8300-intc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xfee012 7>;
};
bsc: memory-controller@fee01e {
compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
reg = <0xfee01e 8>;
};
timer8: timer@ffff80 {
compatible = "renesas,8bit-timer";
reg = <0xffff80 10>;
interrupts = <36 0>;
clocks = <&fclk>;
clock-names = "fck";
};
timer16: timer@ffff68 {
compatible = "renesas,16bit-timer";
reg = <0xffff68 8>, <0xffff60 8>;
interrupts = <24 0>;
renesas,channel = <0>;
clocks = <&fclk>;
clock-names = "fck";
};
sci0: serial@ffffb0 {
compatible = "renesas,sci";
reg = <0xffffb0 8>;
interrupts = <52 0>, <53 0>, <54 0>, <55 0>;
clocks = <&fclk>;
clock-names = "sci_ick";
};
sci1: serial@ffffb8 {
compatible = "renesas,sci";
reg = <0xffffb8 8>;
interrupts = <56 0>, <57 0>, <58 0>, <59 0>;
clocks = <&fclk>;
clock-names = "sci_ick";
};
};
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