path: root/arch/arm64/boot/dts/renesas/r8a77995.dtsi

/*
 * Device Tree Source for the r8a77995 SoC
 *
 * Copyright (C) 2016 Renesas Electronics Corp.
 * Copyright (C) 2017 Glider bvba
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77995-sysc.h>

/ {
	compatible = "renesas,r8a77995";
	#address-cells = <2>;
	#size-cells = <2>;

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a53_0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			device_type = "cpu";
			power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		L2_CA53: cache-controller-1 {
			compatible = "cache";
			power-domains = <&sysc R8A77995_PD_CA53_SCU>;
			cache-unified;
			cache-level = <2>;
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a77995-wdt",
				     "renesas,rcar-gen3-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 9>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 10>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 21>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
		};

		gpio6: gpio@e6055400 {
			compatible = "renesas,gpio-r8a77995",
				     "renesas,rcar-gen3-gpio",
				     "renesas,gpio-rcar";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 14>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 906>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 906>;
		};

		pfc: pin-controller@e6060000 {
			compatible = "renesas,pfc-r8a77995";
			reg = <0 0xe6060000 0 0x508>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a77995-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a77995-rst";
			reg = <0 0xe6160000 0 0x0200>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a77995-sysc";
			reg = <0 0xe6180000 0 0x0400>;
			#power-domain-cells = <1>;
		};

		intc_ex: interrupt-controller@e61c0000 {
			compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0 0xe61c0000 0 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 407>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 407>;
		};

		i2c0: i2c@e6500000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a77995",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe6500000 0 0x40>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 931>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 931>;
			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
			       <&dmac2 0x91>, <&dmac2 0x90>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c1: i2c@e6508000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a77995",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 930>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 930>;
			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
			       <&dmac2 0x93>, <&dmac2 0x92>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c2: i2c@e6510000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a77995",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe6510000 0 0x40>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 929>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 929>;
			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
			       <&dmac2 0x95>, <&dmac2 0x94>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c3: i2c@e66d0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a77995",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe66d0000 0 0x40>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 928>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 928>;
			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
			dma-names = "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		canfd: can@e66c0000 {
			compatible = "renesas,r8a77995-canfd",
				     "renesas,rcar-gen3-canfd";
			reg = <0 0xe66c0000 0 0x8000>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 914>,
			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
			       <&can_clk>;
			clock-names = "fck", "canfd", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
			assigned-clock-rates = <40000000>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 914>;
			status = "disabled";

			channel0 {
				status = "disabled";
			};

			channel1 {
				status = "disabled";
			};
		};

		dmac0: dma-controller@e6700000 {
			compatible = "renesas,dmac-r8a77995",
				     "renesas,rcar-dmac";
			reg = <0 0xe6700000 0 0x10000>;
			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7";
			clocks = <&cpg CPG_MOD 219>;
			clock-names = "fck";
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 219>;
			#dma-cells = <1>;
			dma-channels = <8>;
		};

		dmac1: dma-controller@e7300000 {
			compatible = "renesas,dmac-r8a77995",
				     "renesas,rcar-dmac";
			reg = <0 0xe7300000 0 0x10000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7";
			clocks = <&cpg CPG_MOD 218>;
			clock-names = "fck";
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 218>;
			#dma-cells = <1>;
			dma-channels = <8>;
		};

		dmac2: dma-controller@e7310000 {
			compatible = "renesas,dmac-r8a77995",
				     "renesas,rcar-dmac";
			reg = <0 0xe7310000 0 0x10000>;
			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7";
			clocks = <&cpg CPG_MOD 217>;
			clock-names = "fck";
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 217>;
			#dma-cells = <1>;
			dma-channels = <8>;
		};

		ipmmu_ds0: mmu@e6740000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xe6740000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 0>;
			#iommu-cells = <1>;
		};

		ipmmu_ds1: mmu@e7740000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xe7740000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 1>;
			#iommu-cells = <1>;
		};

		ipmmu_hc: mmu@e6570000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xe6570000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 2>;
			#iommu-cells = <1>;
		};

		ipmmu_mm: mmu@e67b0000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xe67b0000 0 0x1000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
		};

		ipmmu_mp: mmu@ec670000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xec670000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 4>;
			#iommu-cells = <1>;
		};

		ipmmu_pv0: mmu@fd800000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xfd800000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 6>;
			#iommu-cells = <1>;
		};

		ipmmu_rt: mmu@ffc80000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xffc80000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 10>;
			#iommu-cells = <1>;
		};

		ipmmu_vc0: mmu@fe6b0000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xfe6b0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 12>;
			#iommu-cells = <1>;
		};

		ipmmu_vi0: mmu@febd0000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xfebd0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 14>;
			#iommu-cells = <1>;
		};

		ipmmu_vp0: mmu@fe990000 {
			compatible = "renesas,ipmmu-r8a77995";
			reg = <0 0xfe990000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 16>;
			#iommu-cells = <1>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a77995",
				     "renesas,etheravb-rcar-gen3";
			reg = <0 0xe6800000 0 0x800>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14", "ch15",
					  "ch16", "ch17", "ch18", "ch19",
					  "ch20", "ch21", "ch22", "ch23",
					  "ch24";
			clocks = <&cpg CPG_MOD 812>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 812>;
			phy-mode = "rgmii";
			iommus = <&ipmmu_ds0 16>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@e6c30000 {
			compatible = "renesas,can-r8a77995",
				     "renesas,rcar-gen3-can";
			reg = <0 0xe6c30000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 916>,
			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
			       <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
			assigned-clock-rates = <40000000>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 916>;
			status = "disabled";
		};

		can1: can@e6c38000 {
			compatible = "renesas,can-r8a77995",
				     "renesas,rcar-gen3-can";
			reg = <0 0xe6c38000 0 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>,
			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
			       <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
			assigned-clock-rates = <40000000>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			status = "disabled";
		};

		pwm0: pwm@e6e30000 {
			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
			reg = <0 0xe6e30000 0 0x8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			status = "disabled";
		};

		pwm1: pwm@e6e31000 {
			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
			reg = <0 0xe6e31000 0 0x8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			status = "disabled";
		};

		pwm2: pwm@e6e32000 {
			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
			reg = <0 0xe6e32000 0 0x8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			status = "disabled";
		};

		pwm3: pwm@e6e33000 {
			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
			reg = <0 0xe6e33000 0 0x8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			status = "disabled";
		};

		scif2: serial@e6e88000 {
			compatible = "renesas,scif-r8a77995",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e88000 0 64>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>,
				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
			       <&dmac2 0x13>, <&dmac2 0x12>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 310>;
			status = "disabled";
		};

		vin4: video@e6ef4000 {
			compatible = "renesas,vin-r8a77995";
			reg = <0 0xe6ef4000 0 0x1000>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 807>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 807>;
			renesas,id = <4>;
			status = "disabled";
		};

		ohci0: usb@ee080000 {
			compatible = "generic-ohci";
			reg = <0 0xee080000 0 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";
		};

		ehci0: usb@ee080100 {
			compatible = "generic-ehci";
			reg = <0 0xee080100 0 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			companion = <&ohci0>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";
		};

		usb2_phy0: usb-phy@ee080200 {
			compatible = "renesas,usb2-phy-r8a77995",
				     "renesas,rcar-gen3-usb2-phy";
			reg = <0 0xee080200 0 0x700>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			#phy-cells = <0>;
			status = "disabled";
		};

		sdhi2: sd@ee140000 {
			compatible = "renesas,sdhi-r8a77995",
				     "renesas,rcar-gen3-sdhi";
			reg = <0 0xee140000 0 0x2000>;
			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 312>;
			max-frequency = <200000000>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 312>;
			status = "disabled";
		};

		gic: interrupt-controller@f1010000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1010000 0 0x1000>,
			      <0x0 0xf1020000 0 0x20000>,
			      <0x0 0xf1040000 0 0x20000>,
			      <0x0 0xf1060000 0 0x20000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 408>;
		};

		vspbs: vsp@fe960000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfe960000 0 0x8000>;
			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 627>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 627>;
			renesas,fcp = <&fcpvb0>;
		};

		vspd0: vsp@fea20000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea20000 0 0x8000>;
			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 623>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 623>;
			renesas,fcp = <&fcpvd0>;
		};

		vspd1: vsp@fea28000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea28000 0 0x8000>;
			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 622>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 622>;
			renesas,fcp = <&fcpvd1>;
		};

		fcpvb0: fcp@fe96f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfe96f000 0 0x200>;
			clocks = <&cpg CPG_MOD 607>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 607>;
			iommus = <&ipmmu_vp0 5>;
		};

		fcpvd0: fcp@fea27000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfea27000 0 0x200>;
			clocks = <&cpg CPG_MOD 603>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 603>;
			iommus = <&ipmmu_vi0 8>;
		};

		fcpvd1: fcp@fea2f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfea2f000 0 0x200>;
			clocks = <&cpg CPG_MOD 602>;
			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
			resets = <&cpg 602>;
			iommus = <&ipmmu_vi0 9>;
		};

		du: display@feb00000 {
			compatible = "renesas,du-r8a77995";
			reg = <0 0xfeb00000 0 0x80000>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 724>,
				 <&cpg CPG_MOD 723>;
			clock-names = "du.0", "du.1";
			vsps = <&vspd0 0 &vspd1 0>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					du_out_rgb: endpoint {
					};
				};

				port@1 {
					reg = <1>;
					du_out_lvds0: endpoint {
					};
				};

				port@2 {
					reg = <2>;
					du_out_lvds1: endpoint {
					};
				};
			};
		};

		prr: chipid@fff00044 {
			compatible = "renesas,prr";
			reg = <0 0xfff00044 0 4>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
	};
};