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/*
* Copyright (c) 2017 MediaTek Inc.
* Author: YT Shen <yt.shen@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt2712";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&cpu2>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
baud_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
sys_clk: dummyclk {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
};
uart5: serial@1000f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x1000f000 0 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
sysirq: interrupt-controller@10220a80 {
compatible = "mediatek,mt2712-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220a80 0 0x40>;
};
gic: interrupt-controller@10510000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10510000 0 0x10000>,
<0 0x10520000 0 0x20000>,
<0 0x10540000 0 0x20000>,
<0 0x10560000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11019000 0 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
};
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