blob: 3da78cfc5a94b6563d8276a0daa149edd3d9f954 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/system_misc.h>
#include <asm/proc-fns.h>
#include <asm/mach-types.h>
static void __iomem *wdog_base;
/*
* Reset the system. It is called by machine_restart().
*/
void mxc_restart(char mode, const char *cmd)
{
unsigned int wcr_enable;
if (cpu_is_mx1()) {
wcr_enable = (1 << 0);
} else {
struct clk *clk;
clk = clk_get_sys("imx2-wdt.0", NULL);
if (!IS_ERR(clk))
clk_prepare_enable(clk);
wcr_enable = (1 << 2);
}
/* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
/* delay to allow the serial port to show the message */
mdelay(50);
/* we'll take a jump through zero as a poor second */
soft_restart(0);
}
void mxc_arch_reset_init(void __iomem *base)
{
wdog_base = base;
}
|
