summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/qcom-ipq4019.dtsi
blob: 1008dfbcb9728eb16b03eec99bcd8755a3c2ad14 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Qualcomm Technologies, Inc. IPQ4019";
	compatible = "qcom,ipq4019";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		smem_region: smem@87e00000 {
			reg = <0x87e00000 0x080000>;
			no-map;
		};

		tz@87e80000 {
			reg = <0x87e80000 0x180000>;
			no-map;
		};
	};

	aliases {
		spi0 = &blsp1_spi1;
		spi1 = &blsp1_spi2;
		i2c0 = &blsp1_i2c3;
		i2c1 = &blsp1_i2c4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			reg = <0x0>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			reg = <0x1>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			reg = <0x2>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			reg = <0x3>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-48000000 {
			opp-hz = /bits/ 64 <48000000>;
			clock-latency-ns = <256000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <256000>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <256000>;
		};
		opp-716000000 {
			opp-hz = /bits/ 64 <716000000>;
			clock-latency-ns = <256000>;
 		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};

		xo: xo {
			compatible = "fixed-clock";
			clock-frequency = <48000000>;
			#clock-cells = <0>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-ipq4019";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <48000000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>,
			<0x0b002000 0x1000>;
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-ipq4019";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0x1800000 0x60000>;
		};

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x22000 0x140>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
			status = "disabled";
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq4019-pinctrl";
			reg = <0x01000000 0x300000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		cryptobam: dma@8e04000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x08e04000 0x20000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,controlled-remotely;
			status = "disabled";
		};

		crypto@8e3a000 {
			compatible = "qcom,crypto-v5.1";
			reg = <0x08e3a000 0x6000>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 2>, <&cryptobam 3>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		acc0: clock-controller@b088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
		};

		acc1: clock-controller@b098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
		};

		acc2: clock-controller@b0a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
		};

		acc3: clock-controller@b0b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
		};

		saw0: regulator@b089000 {
			compatible = "qcom,saw2";
			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
                        regulator;
		};

		saw1: regulator@b099000 {
			compatible = "qcom,saw2";
			reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		saw2: regulator@b0a9000 {
			compatible = "qcom,saw2";
			reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		saw3: regulator@b0b9000 {
			compatible = "qcom,saw2";
			reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
		};

		watchdog@b017000 {
			compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
			reg = <0xb017000 0x40>;
			clocks = <&sleep_clk>;
			timeout-sec = <10>;
			status = "disabled";
		};

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		pcie0: pci@40000000 {
			compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
			reg =  <0x40000000 0xf1d
				0x40000f20 0xa8
				0x80000 0x2000
				0x40100000 0x1000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
				 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
			clocks = <&gcc GCC_PCIE_AHB_CLK>,
				 <&gcc GCC_PCIE_AXI_M_CLK>,
				 <&gcc GCC_PCIE_AXI_S_CLK>;
			clock-names = "aux",
				      "master_bus",
				      "slave_bus";

			resets = <&gcc PCIE_AXI_M_ARES>,
				 <&gcc PCIE_AXI_S_ARES>,
				 <&gcc PCIE_PIPE_ARES>,
				 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
				 <&gcc PCIE_AXI_S_XPU_ARES>,
				 <&gcc PCIE_PARF_XPU_ARES>,
				 <&gcc PCIE_PHY_ARES>,
				 <&gcc PCIE_AXI_M_STICKY_ARES>,
				 <&gcc PCIE_PIPE_STICKY_ARES>,
				 <&gcc PCIE_PWR_ARES>,
				 <&gcc PCIE_AHB_ARES>,
				 <&gcc PCIE_PHY_AHB_ARES>;
			reset-names = "axi_m",
				      "axi_s",
				      "pipe",
				      "axi_m_vmid",
				      "axi_s_xpu",
				      "parf",
				      "phy",
				      "axi_m_sticky",
				      "pipe_sticky",
				      "pwr",
				      "ahb",
				      "phy_ahb";

			status = "disabled";
		};

		qpic_bam: dma@7984000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x7984000 0x1a000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_QPIC_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		nand: qpic-nand@79b0000 {
			compatible = "qcom,ipq4019-nand";
			reg = <0x79b0000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "disabled";

			nand@0 {
				reg = <0>;

				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;
				nand-bus-width = <8>;
			};
		};

		wifi0: wifi@a000000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa000000 0x200000>;
			resets = <&gcc WIFI0_CPU_INIT_RESET>,
				 <&gcc WIFI0_RADIO_SRIF_RESET>,
				 <&gcc WIFI0_RADIO_WARM_RESET>,
				 <&gcc WIFI0_RADIO_COLD_RESET>,
				 <&gcc WIFI0_CORE_WARM_RESET>,
				 <&gcc WIFI0_CORE_COLD_RESET>;
			reset-names = "wifi_cpu_init", "wifi_radio_srif",
				      "wifi_radio_warm", "wifi_radio_cold",
				      "wifi_core_warm", "wifi_core_cold";
			clocks = <&gcc GCC_WCSS2G_CLK>,
				 <&gcc GCC_WCSS2G_REF_CLK>,
				 <&gcc GCC_WCSS2G_RTC_CLK>;
			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
				      "wifi_wcss_rtc";
			interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
					   "msi4",  "msi5",  "msi6",  "msi7",
					   "msi8",  "msi9", "msi10", "msi11",
					  "msi12", "msi13", "msi14", "msi15",
					  "legacy";
			status = "disabled";
		};

		wifi1: wifi@a800000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa800000 0x200000>;
			resets = <&gcc WIFI1_CPU_INIT_RESET>,
				 <&gcc WIFI1_RADIO_SRIF_RESET>,
				 <&gcc WIFI1_RADIO_WARM_RESET>,
				 <&gcc WIFI1_RADIO_COLD_RESET>,
				 <&gcc WIFI1_CORE_WARM_RESET>,
				 <&gcc WIFI1_CORE_COLD_RESET>;
			reset-names = "wifi_cpu_init", "wifi_radio_srif",
				      "wifi_radio_warm", "wifi_radio_cold",
				      "wifi_core_warm", "wifi_core_cold";
			clocks = <&gcc GCC_WCSS5G_CLK>,
				 <&gcc GCC_WCSS5G_REF_CLK>,
				 <&gcc GCC_WCSS5G_RTC_CLK>;
			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
				      "wifi_wcss_rtc";
			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
					   "msi4",  "msi5",  "msi6",  "msi7",
					   "msi8",  "msi9", "msi10", "msi11",
					  "msi12", "msi13", "msi14", "msi15",
					  "legacy";
			status = "disabled";
		};
	};
};