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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the Freecom FSG-3 router.
* This machine is based on IXP425.
* This device tree is inspired by the board file by Rod Whitby.
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Freecom FSG-3";
compatible = "freecom,fsg-3", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
/* 64 MB memory */
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
/* Boot from the first partition on the hard drive */
bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
stdout-path = "uart0:115200n8";
};
aliases {
serial0 = &uart0;
};
gpio_keys {
compatible = "gpio-keys";
button-sync {
wakeup-source;
/* Closest approximation of what the key should do */
linux,code = <KEY_CONNECT>;
label = "sync";
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
};
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
label = "reset";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};
button-usb {
wakeup-source;
/* Unplug USB, closest approximation of what the key should do */
linux,code = <KEY_EJECTCD>;
label = "usb";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
hwmon@28 {
/*
* Temperature sensor and fan control chip.
*
* TODO: create a proper device tree binding for
* the sensor and temperature zone and create a
* zone with fan control.
*/
compatible = "winbond,w83781d";
reg = <0x28>;
};
rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 4 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x400000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x3e0000 */
fis-index-block = <0x1f>;
};
};
};
pci@c0000000 {
status = "ok";
/*
* Written based on the FSG-3 PCI boardfile.
* We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 12 */
<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
/* IDSEL 13 */
<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
/* IDSEL 14 */
<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
};
/* EthB */
ethernet@c8009000 {
status = "ok";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy5>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
};
/* EthC */
ethernet@c800a000 {
status = "ok";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
phy-handle = <&phy4>;
};
};
};
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