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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas MSIOF SPI controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
oneOf:
- items:
- const: renesas,msiof-sh73a0 # SH-Mobile AG5
- const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
# device
- items:
- enum:
- renesas,msiof-r8a7743 # RZ/G1M
- renesas,msiof-r8a7744 # RZ/G1N
- renesas,msiof-r8a7745 # RZ/G1E
- renesas,msiof-r8a77470 # RZ/G1C
- renesas,msiof-r8a7790 # R-Car H2
- renesas,msiof-r8a7791 # R-Car M2-W
- renesas,msiof-r8a7792 # R-Car V2H
- renesas,msiof-r8a7793 # R-Car M2-N
- renesas,msiof-r8a7794 # R-Car E2
- const: renesas,rcar-gen2-msiof # generic R-Car Gen2 and RZ/G1
# compatible device
- items:
- enum:
- renesas,msiof-r8a774a1 # RZ/G2M
- renesas,msiof-r8a774b1 # RZ/G2N
- renesas,msiof-r8a774c0 # RZ/G2E
- renesas,msiof-r8a7795 # R-Car H3
- renesas,msiof-r8a7796 # R-Car M3-W
- renesas,msiof-r8a77965 # R-Car M3-N
- renesas,msiof-r8a77970 # R-Car V3M
- renesas,msiof-r8a77980 # R-Car V3H
- renesas,msiof-r8a77990 # R-Car E3
- renesas,msiof-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2
# compatible device
- items:
- const: renesas,sh-msiof # deprecated
reg:
minItems: 1
maxItems: 2
oneOf:
- items:
- description: CPU and DMA engine registers
- items:
- description: CPU registers
- description: DMA engine registers
interrupts:
maxItems: 1
clocks:
maxItems: 1
num-cs:
description: |
Total number of chip selects (default is 1).
Up to 3 native chip selects are supported:
0: MSIOF_SYNC
1: MSIOF_SS1
2: MSIOF_SS2
Hardware limitations related to chip selects:
- Native chip selects are always deasserted in between transfers
that are part of the same message. Use cs-gpios to work around
this.
- All slaves using native chip selects must use the same spi-cs-high
configuration. Use cs-gpios to work around this.
- When using GPIO chip selects, at least one native chip select must
be left unused, as it will be driven anyway.
minimum: 1
maximum: 3
default: 1
dmas:
minItems: 2
maxItems: 4
dma-names:
minItems: 2
maxItems: 4
items:
enum: [ tx, rx ]
renesas,dtdl:
description: delay sync signal (setup) in transmit mode.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum:
- 0 # no bit delay
- 50 # 0.5-clock-cycle delay
- 100 # 1-clock-cycle delay
- 150 # 1.5-clock-cycle delay
- 200 # 2-clock-cycle delay
renesas,syncdl:
description: delay sync signal (hold) in transmit mode
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum:
- 0 # no bit delay
- 50 # 0.5-clock-cycle delay
- 100 # 1-clock-cycle delay
- 150 # 1.5-clock-cycle delay
- 200 # 2-clock-cycle delay
- 300 # 3-clock-cycle delay
renesas,tx-fifo-size:
# deprecated for soctype-specific bindings
description: |
Override the default TX fifo size. Unit is words. Ignored if 0.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
default: 64
renesas,rx-fifo-size:
# deprecated for soctype-specific bindings
description: |
Override the default RX fifo size. Unit is words. Ignored if 0.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
default: 64
required:
- compatible
- reg
- interrupts
- '#address-cells'
- '#size-cells'
examples:
- |
#include <dt-bindings/clock/r8a7791-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
};
|
