summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
blob: c7c4347a769a88395c2358825cec5b906f5c4726 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
TI SOC ECAP based APWM controller

Required properties:
- compatible: Must be "ti,<soc>-ecap".
  for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
  for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
  for da850  - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
  for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
  for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap";
  for am654  - compatible = "ti,am654-ecap", "ti,am3352-ecap";
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
  the cells format. The PWM channel index ranges from 0 to 4. The only third
  cell flag supported by this binding is PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.

Optional properties:
- clocks: Handle to the ECAP's functional clock.
- clock-names: Must be set to "fck".

Example:

ecap0: ecap@48300100 { /* ECAP on am33xx */
	compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x48300100 0x80>;
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
};

ecap0: ecap@48300100 { /* ECAP on am4372 */
	compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x48300100 0x80>;
	ti,hwmods = "ecap0";
	clocks = <&l4ls_gclk>;
	clock-names = "fck";
};

ecap0: ecap@1f06000 { /* ECAP on da850 */
	compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
	#pwm-cells = <3>;
	reg = <0x1f06000 0x80>;
};

ecap0: ecap@4843e100 {
	compatible = "ti,dra746-ecap", "ti,am3352-ecap";
	#pwm-cells = <3>;
	reg = <0x4843e100 0x80>;
	clocks = <&l4_root_clk_div>;
	clock-names = "fck";
};