1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,drif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
maintainers:
- Ramesh Shanmugasundaram <rashanmu@gmail.com>
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
description: |
R-Car Gen3 DRIF is a SPI like receive only slave device. A general
representation of DRIF interfacing with a master device is shown below.
+---------------------+ +---------------------+
| |-----SCK------->|CLK |
| Master |-----SS-------->|SYNC DRIFn (slave) |
| |-----SD0------->|D0 |
| |-----SD1------->|D1 |
+---------------------+ +---------------------+
As per datasheet, each DRIF channel (drifn) is made up of two internal
channels (drifn0 & drifn1). These two internal channels share the common
CLK & SYNC. Each internal channel has its own dedicated resources like
irq, dma channels, address space & clock. This internal split is not
visible to the external master device.
The device tree model represents each internal channel as a separate node.
The internal channels sharing the CLK & SYNC are tied together by their
phandles using a property called "renesas,bonding". For the rest of
the documentation, unless explicitly stated, the word channel implies an
internal channel.
When both internal channels are enabled they need to be managed together
as one (i.e.) they cannot operate alone as independent devices. Out of the
two, one of them needs to act as a primary device that accepts common
properties of both the internal channels. This channel is identified by a
property called "renesas,primary-bond".
To summarize,
* When both the internal channels that are bonded together are enabled,
the zeroth channel is selected as primary-bond. This channels accepts
properties common to all the members of the bond.
* When only one of the bonded channels need to be enabled, the property
"renesas,bonding" or "renesas,primary-bond" will have no effect. That
enabled channel can act alone as any other independent device.
properties:
compatible:
items:
- enum:
- renesas,r8a7795-drif # R-Car H3
- renesas,r8a7796-drif # R-Car M3-W
- renesas,r8a77965-drif # R-Car M3-N
- renesas,r8a77990-drif # R-Car E3
- const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
items:
- const: fck
resets:
maxItems: 1
dmas:
minItems: 1
maxItems: 2
dma-names:
minItems: 1
maxItems: 2
items:
- const: rx
- const: rx
renesas,bonding:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle to the other internal channel of DRIF
power-domains:
maxItems: 1
renesas,primary-bond:
type: boolean
description:
Indicates that the channel acts as primary among the bonded channels.
port:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
description:
Child port node corresponding to the data input. The port node must
contain at least one endpoint.
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
properties:
sync-active:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
Indicates sync signal polarity, 0/1 for low/high respectively.
This property maps to SYNCAC bit in the hardware manual. The
default is 1 (active high).
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- dmas
- dma-names
- renesas,bonding
- power-domains
allOf:
- if:
required:
- renesas,primary-bond
then:
required:
- pinctrl-0
- pinctrl-names
- port
- if:
required:
- port
then:
required:
- pinctrl-0
- pinctrl-names
else:
properties:
pinctrl-0: false
pinctrl-names: false
additionalProperties: false
examples:
# Example with both internal channels enabled.
#
# When interfacing with a third party tuner device with two data pins as shown
# below.
#
# +---------------------+ +---------------------+
# | |-----SCK------->|CLK |
# | Master |-----SS-------->|SYNC DRIFn (slave) |
# | |-----SD0------->|D0 |
# | |-----SD1------->|D1 |
# +---------------------+ +---------------------+
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
drif00: rif@e6f40000 {
compatible = "renesas,r8a7795-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x64>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
renesas,bonding = <&drif01>;
resets = <&cpg 515>;
renesas,primary-bond;
pinctrl-0 = <&drif0_pins>;
pinctrl-names = "default";
port {
drif0_ep: endpoint {
remote-endpoint = <&tuner_ep>;
};
};
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a7795-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x64>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
renesas,bonding = <&drif00>;
resets = <&cpg 514>;
};
};
# Example with internal channel 1 alone enabled.
#
# When interfacing with a third party tuner device with one data pin as shown
# below.
#
# +---------------------+ +---------------------+
# | |-----SCK------->|CLK |
# | Master |-----SS-------->|SYNC DRIFn (slave) |
# | | |D0 (unused) |
# | |-----SD-------->|D1 |
# +---------------------+ +---------------------+
- |
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7795-sysc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
drif10: rif@e6f60000 {
compatible = "renesas,r8a7795-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x64>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a7795-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x64>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
pinctrl-0 = <&drif1_pins>;
pinctrl-names = "default";
port {
drif1_ep: endpoint {
remote-endpoint = <&tuner_ep1>;
sync-active = <0>;
};
};
};
};
...
|
