summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/display/msm/mdp.txt
blob: 0833edaba4c3704717726af66a105d0aade1d4ea (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Qualcomm adreno/snapdragon display controller

Required properties:
- compatible:
  * "qcom,mdp" - mdp4
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the display controller.
- connectors: array of phandles for output device(s)
- clocks: device clocks
  See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
  * "core_clk"
  * "iface_clk"
  * "src_clk"
  * "hdmi_clk"
  * "mpd_clk"

Optional properties:
- gpus: phandle for gpu device
- clock-names: the following clocks are optional:
  * "lut_clk"

Example:

/ {
	...

	mdp: qcom,mdp@5100000 {
		compatible = "qcom,mdp";
		reg = <0x05100000 0xf0000>;
		interrupts = <GIC_SPI 75 0>;
		connectors = <&hdmi>;
		gpus = <&gpu>;
		clock-names =
		    "core_clk",
		    "iface_clk",
		    "lut_clk",
		    "src_clk",
		    "hdmi_clk",
		    "mdp_clk";
		clocks =
		    <&mmcc MDP_SRC>,
		    <&mmcc MDP_AHB_CLK>,
		    <&mmcc MDP_LUT_CLK>,
		    <&mmcc TV_SRC>,
		    <&mmcc HDMI_TV_CLK>,
		    <&mmcc MDP_TV_CLK>;
	};
};