summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
blob: a19a6cc375ed7280a016a31c35dae8aa3734d244 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Mediatek DSI Device
===================

The Mediatek DSI function block is a sink of the display subsystem and can
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
channel output.

Required properties:
- compatible: "mediatek,<chip>-dsi"
  the supported chips are mt2701, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: must contain "engine", "digital", and "hs"
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy"
- port: Output port node with endpoint definitions as described in
  Documentation/devicetree/bindings/graph.txt. This port should be connected
  to the input port of an attached DSI panel or DSI-to-eDP encoder chip.

MIPI TX Configuration Module
============================

The MIPI TX configuration module controls the MIPI D-PHY.

Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
  the supported chips are mt2701, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
- #clock-cells: must be <0>;
- #phy-cells: must be <0>.

Example:

mipi_tx0: mipi-dphy@10215000 {
	compatible = "mediatek,mt8173-mipi-tx";
	reg = <0 0x10215000 0 0x1000>;
	clocks = <&clk26m>;
	clock-output-names = "mipi_tx0_pll";
	#clock-cells = <0>;
	#phy-cells = <0>;
};

dsi0: dsi@1401b000 {
	compatible = "mediatek,mt8173-dsi";
	reg = <0 0x1401b000 0 0x1000>;
	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
		 <&mipi_tx0>;
	clock-names = "engine", "digital", "hs";
	phys = <&mipi_tx0>;
	phy-names = "dphy";

	port {
		dsi0_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};