blob: c56c7553c7300213cc2a12865eb0589a269b6fce (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
Binding for the HSDK Generic PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: should be "snps,hsdk-<name>-pll-clock"
"snps,hsdk-core-pll-clock"
"snps,hsdk-gp-pll-clock"
"snps,hsdk-hdmi-pll-clock"
- reg : should contain base register location and length.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.
Example:
input_clk: input-clk {
clock-frequency = <33333333>;
compatible = "fixed-clock";
#clock-cells = <0>;
};
cpu_clk: cpu-clk@0 {
compatible = "snps,hsdk-core-pll-clock";
reg = <0x00 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
};
|