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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bitmain BM1880 Clock Controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
The Bitmain BM1880 clock controller generates and supplies clock to
various peripherals within the SoC.
This binding uses common clock bindings
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
properties:
compatible:
const: bitmain,bm1880-clk
reg:
items:
- description: pll registers
- description: system registers
reg-names:
items:
- const: pll
- const: sys
clocks:
maxItems: 1
clock-names:
const: osc
'#clock-cells':
const: 1
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
# Clock controller node:
- |
clk: clock-controller@e8 {
compatible = "bitmain,bm1880-clk";
reg = <0xe8 0x0c>, <0x800 0xb0>;
reg-names = "pll", "sys";
clocks = <&osc>;
clock-names = "osc";
#clock-cells = <1>;
};
# Example UART controller node that consumes clock generated by the clock controller:
- |
uart0: serial@58018000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x58018000 0x0 0x2000>;
clocks = <&clk 45>, <&clk 46>;
clock-names = "baudclk", "apb_pclk";
interrupts = <0 9 4>;
reg-shift = <2>;
reg-io-width = <4>;
};
...
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