Age | Commit message (Collapse) | Author | Files | Lines | |
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2022-03-22 | rseq/selftests: Add support for RISC-V | Vincent Chen | 1 | -0/+677 | |
Add support for RISC-V in the rseq selftests, which covers both 64-bit and 32-bit ISA with little endian mode. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Tested-by: Eric Lin <eric.lin@sifive.com> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |