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2022-06-06ASoC: fsl_sai: Add support for i.MX8MNShengjiu Wang1-0/+1
The SAI module on i.MX8MN is almost same as i.MX8MP, So reuse same soc data as i.MX8MP. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1653966123-28217-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16ASoC: fsl_sai: Add support for i.MX8ULPShengjiu Wang1-1/+13
Add i.MX8ULP specific soc data, the max register is FSL_SAI_RTCAP the IP version is also 0x0301, So version can't be used for the condition of register FSL_SAI_MCTL setting. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1652688372-10274-4-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16ASoC: fsl_sai: Add support for i.MX8M PlusShengjiu Wang1-0/+12
Add i.MX8M Plus specific soc data, the max register is FSL_SAI_MDIV. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1652688372-10274-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16ASoC: fsl_sai: Add support for i.MX8MMShengjiu Wang1-0/+17
On i.MX8MM the max register is FSL_SAI_MCTL, which is different with previous platform, so add max_register in soc data to distinguish platforms. And add specific soc data for i.MX8MM Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1652688372-10274-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-06ASoC: fsl_sai: fix 1:1 bclk:mclk ratio supportAhmad Fatoum1-1/+1
Refactoring in commit a50b7926d015 ("ASoC: fsl_sai: implement 1:1 bclk:mclk ratio support") led to the bypass never happening as (ratio = 1) was caught in the existing if (ratio & 1) continue; check. The correct check sequence instead is: - skip all ratios lower than one and higher than 512 - skip all odd ratios except for 1:1 - skip 1:1 ratio if and only if !support_1_1_ratio And for all others, calculate the appropriate divider. Adjust the code to facilitate this. Fixes: a50b7926d015 ("ASoC: fsl_sai: implement 1:1 bclk:mclk ratio support") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220405155731.745413-1-a.fatoum@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: implement 1:1 bclk:mclk ratio supportAhmad Fatoum1-2/+15
With higher channel counts, we may need higher clock rates. Starting with SAI v3.1 (i.MX8MM), we can bypass the divider and get a 1:1 bclk:mclk ratio. Add the necessary support. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-8-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: use DIV_ROUND_CLOSEST() to calculate dividerSascha Hauer1-7/+5
In fsl_sai_set_bclk() we want to calculate the divider that gets us closest to the desired frequency, so use DIV_ROUND_CLOSEST() instead of just doing a clk_rate/freq. Also discard invalid ratios earlier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-7-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: Use better variable namesSascha Hauer1-8/+9
"ret" is normally used as a variable name for return values. In fsl_sai_set_bclk() it stores the difference between the desired rate and the rate we can archieve, so rename it to "diff". Also rename "savesub" to "bestdiff" as that stores the best difference we have found. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-6-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: store full version instead of major/minorSascha Hauer1-5/+3
The driver tests for the hardware revision being newer than 3.1 with (sai->verid.major >= 3 && sai->verid.minor >= 1). The result is obviously wrong for hardware revision 4.0. Fix this by storing the full version in a single variable and comparing to that one. No practical change at the moment as there is no 4.0 ip version currently. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-5-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: simplify register poking in fsl_sai_set_bclkAhmad Fatoum1-16/+13
Depending on SAI synchronization mode, the same value is either written to FSL_SAI_TCR2 or FSL_SAI_RCR2 or nothing is written at all. As the computation is the same either way, factor it out to make it clearer what the difference is. No functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-4-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: simplify irq return valueSascha Hauer1-7/+4
Instead of using a boolean "irq_none" to describe the interrupt handlers return value use a variable of type irqreturn_t and return it directly. No functional change. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-3-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: Drop unnecessary definesSascha Hauer1-10/+6
The fsl_sai driver has FSL_FMT_TRANSMITTER and FSL_FMT_RECEIVER defines which are used in a single function only then are then only translated into a bool 'tx' variable. Drop the defines and pass the boolean value directly to fsl_sai_set_dai_sysclk_tr(). No functional change. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-2-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-28ASoC: fsl: Drop unused argument from imx_pcm_dma_init()Sascha Hauer1-1/+1
Since 70d435ba1cd ("ASoC: imx-pcm-dma: simplify pcm_config") the size argument to imx_pcm_dma_init() is unused, so drop it. Also remove the now unused defines that the users of imx_pcm_dma_init() used to pass the size argument Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220223130625.3430589-1-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-08ASoC: fsl_sai: Enable combine mode softSascha Hauer1-0/+9
The fsl_sai driver calculates the number of pins used and enables multiple channels if necessary. This means the SAI expects data in one FIFO per pin. The SDMA engine only services a single FIFO, so multi pin support doesn't work at all. This patch enables the software combine mode in chips that support it. With this the SAI presents only a single FIFO to the outside and distributes the data into the different FIFOs internally. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220111081518.982437-1-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-22ASoC: fsl_sai: Update to modern clocking terminologyMark Brown1-17/+17
As part of moving to remove the old style defines for the bus clocks update the fsl_sai driver to use more modern terminology for clocking. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210921213542.31688-6-broonie@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-10ASoC: fsl_sai: register platform component before registering cpu daiShengjiu Wang1-5/+9
There is no defer probe when adding platform component to snd_soc_pcm_runtime(rtd), the code is in snd_soc_add_pcm_runtime() snd_soc_register_card() -> snd_soc_bind_card() -> snd_soc_add_pcm_runtime() -> adding cpu dai -> adding codec dai -> adding platform component. So if the platform component is not ready at that time, then the sound card still registered successfully, but platform component is empty, the sound card can't be used. As there is defer probe checking for cpu dai component, then register platform component before cpu dai to avoid such issue. Fixes: 435508214942 ("ASoC: Add SAI SoC Digital Audio Interface driver") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1630665006-31437-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-06-21ASoC: fsl_sai: Use devm_platform_get_and_ioremap_resource()Yang Yingliang1-2/+1
Use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210615013922.784296-7-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-22ASoC: fsl_sai: Don't use devm_regmap_init_mmio_clkShengjiu Wang1-16/+32
When there is power domain bind with bus clock, The call flow: devm_regmap_init_mmio_clk - clk_prepare() - clk_pm_runtime_get() cause the power domain of clock always be enabled after regmap_init(). which impact the power consumption. So use devm_regmap_init_mmio instead of devm_regmap_init_mmio_clk, then explicitly enable clock when using by pm_runtime_get(), if CONFIG_PM=n, then fsl_sai_runtime_resume will be explicitly called. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Link: https://lore.kernel.org/r/1616141203-13344-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-10Merge series "drop unneeded snd_soc_dai_set_drvdata" from Julia Lawall ↵Mark Brown1-2/+0
<Julia.Lawall@inria.fr>: snd_soc_dai_set_drvdata is not needed when the set data comes from snd_soc_dai_get_drvdata or dev_get_drvdata. --- sound/soc/fsl/fsl_micfil.c | 2 -- sound/soc/fsl/fsl_sai.c | 2 -- sound/soc/fsl/fsl_xcvr.c | 1 - sound/soc/mxs/mxs-saif.c | 10 ---------- sound/soc/pxa/mmp-sspa.c | 1 - sound/soc/sunxi/sun4i-i2s.c | 2 -- 6 files changed, 18 deletions(-)
2021-03-10ASoC: fsl_sai: Add pm qos cpu latency supportShengjiu Wang1-0/+12
On SoCs such as i.MX7ULP, cpuidle has some levels which may disable system/bus clocks, so need to add pm_qos to prevent cpuidle from entering low level idles and make sure system/bus clocks are enabled when sai is active. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1613983220-5373-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-10ASoC: fsl: drop unneeded snd_soc_dai_set_drvdataJulia Lawall1-2/+0
snd_soc_dai_set_drvdata is not needed when the set data comes from snd_soc_dai_get_drvdata or dev_get_drvdata. The problem was fixed usingthe following semantic patch: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x,y,e; @@ x = dev_get_drvdata(y->dev) ... when != x = e - snd_soc_dai_set_drvdata(y,x); @@ expression x,y,e; @@ x = snd_soc_dai_get_drvdata(y) ... when != x = e - snd_soc_dai_set_drvdata(y,x); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20210213101907.1318496-5-Julia.Lawall@inria.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-21ASoC: fsl: sync parameter naming (rate/sample_bits)Kuninori Morimoto1-4/+4
This patch syncs naming rule. - xxx_rates; + xxx_rate; - xxx_samplebits; + xxx_sample_bits; Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87eeimolh5.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19ASoC: fsl_sai: Correct the clock source for mclk0Shengjiu Wang1-2/+18
On VF610, mclk0 = bus_clk; On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1; On i.MX7ULP, mclk0 = bus_clk; On i.MX8QM/8QXP, mclk0 = bus_clk; On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk; So add variable mclk0_is_mclk1 in fsl_sai_soc_data to distinguish these platforms. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1605768038-4582-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-10-09Merge remote-tracking branch 'asoc/for-5.10' into asoc-nextMark Brown1-91/+199
2020-09-25ASoC: fsl_sai: Instantiate snd_soc_dai_driverShengjiu Wang1-8/+11
Instantiate snd_soc_dai_driver for independent symmetric control. Otherwise the symmetric setting may be overwritten by other instance. Fixes: 08fdf65e37d5 ("ASoC: fsl_sai: Add asynchronous mode support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1600424760-32071-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-17ASoC: fsl_sai: Set MCLK input or output directionShengjiu Wang1-0/+7
SAI support select MCLK direction with version.major > 3 and version.minor > 1, the default direction is input, set it to be output according to DT property. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-4-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-17ASoC: fsl_sai: Add fsl_sai_check_version functionShengjiu Wang1-0/+47
fsl_sai_check_version can help to parse the version info in VERID and PARAM registers. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-17ASoC: fsl_sai: Add new added registers and new bit definitionShengjiu Wang1-0/+23
On i.MX8MQ/i.MX8MN/i.MX8MM platform, the sai IP is upgraded. There are some new registers and new bit definition. This patch is to complete the register list. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-03ASoC: fsl_sai: Set SAI Channel Mode to Output ModeShengjiu Wang1-2/+8
Transmit data pins will output zero when slots are masked or channels are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. When data pins are tri-stated, there is noise on some channels when FS clock value is high and data is read while fsclk is transitioning from high to low. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1599112427-22038-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-03ASoC: fsl_sai: Support multiple data channel enable bitsShengjiu Wang1-18/+12
One data channel is one data line. From imx7ulp, the SAI IP is enhanced to support multiple data channels. If there is only two channels input and slots is 2, then enable one data channel is enough for data transfer. So enable the TCE/RCE and transmit/receive mask register according to the input channels and slots configuration. Move the data channel enablement from startup() to hw_params(). Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1598958068-10552-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-08-24ASoC: fsl_sai: Add -EPROBE_DEFER check for regmap initShengjiu Wang1-1/+1
Regmap initialization may return -EPROBE_DEFER for clock may not be ready, so check -EPROBE_DEFER error type before start another Regmap initialization. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1598255887-1391-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-08-17ASoC: fsl_sai: Replace synchronous check with fsl_sai_dir_is_syncedShengjiu Wang1-24/+16
As new function fsl_sai_dir_is_synced is included for checking if stream is synced by the opposite stream, then replace the existing synchronous checking with this new function. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200805063413.4610-4-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-08-17ASoC: fsl_sai: Drop TMR/RMR settings for synchronous modeShengjiu Wang1-6/+1
Tx synchronous with Rx: The RMR is the word mask register, it is used to mask any word in the frame, it is not relating to clock generation, So it is no need to be changed when Tx is going to be enabled. Rx synchronous with Tx: The TMR is the word mask register, it is used to mask any word in the frame, it is not relating to clock generation, So it is no need to be changed when Rx is going to be enabled. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200805063413.4610-3-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-08-17ASoC: fsl_sai: Refine enable/disable TE/RE sequence in trigger()Shengjiu Wang1-41/+85
Current code enables TCSR.TE and RCSR.RE together, and disable TCSR.TE and RCSR.RE together in trigger(), which only supports one operation mode： 1. Rx synchronous with Tx: TE is last enabled and first disabled Other operation mode need to be considered also: 2. Tx synchronous with Rx: RE is last enabled and first disabled. 3. Asynchronous mode: Tx and Rx are independent. So the enable TCSR.TE and RCSR.RE sequence and the disable sequence need to be refined accordingly for #2 and #3. There is slightly against what RM recommennds with this change. For example in Rx synchronous with Tx mode, case "aplay 1.wav; arecord 2.wav" enable TE before RE. But it should be safe to do so, judging by years of testing results. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200805063413.4610-2-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-31Merge remote-tracking branch 'asoc/for-5.9' into asoc-nextMark Brown1-1/+2
2020-07-31ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASKShengjiu Wang1-2/+3
The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on i.MX7ULP. Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for these platform, the FIFO watermark mask should be updated according to the fifo_depth. Fixes: a860fac42097 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-01ASoC: fsl_sai: Refine regcache usage with pm runtimeShengjiu Wang1-1/+2
When there is dedicated power domain bound with device, after probing the power will be disabled, then registers are not accessible in fsl_sai_dai_probe(), so regcache only need to be enabled in end of probe() and regcache_mark_dirty should be moved to pm runtime resume callback function. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1593412953-10897-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-06ASoC: fsl_sai: Fix exiting path on probing failureOleksandr Suvorov1-5/+17
If the imx-sdma driver is built as a module, the fsl-sai device doesn't disable on probing failure, which causes the warning in the next probing: ================================================================== fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! ================================================================== Disabling the device properly fixes the issue. Fixes: 812ad463e089 ("ASoC: fsl_sai: Add support for runtime pm") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Link: https://lore.kernel.org/r/20200205160436.3813642-1-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-09ASoC: fsl_sai: add IRQF_SHAREDMichael Walle1-1/+2
The LS1028A SoC uses the same interrupt line for adjacent SAIs. Use IRQF_SHARED to be able to use these SAIs simultaneously. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20191128223802.18228-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-17ASoC: fsl_sai: Fix noise when using EDMAMihai Serban1-0/+15
EDMA requires the period size to be multiple of maxburst. Otherwise the remaining bytes are not transferred and thus noise is produced. We can handle this issue by adding a constraint on SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value. Signed-off-by: Mihai Serban <mihai.serban@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190913192807.8423-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-13ASoC: fsl_sai: Implement set_bclk_ratioViorel Suman1-2/+19
This is to allow machine drivers to set a certain bitclk rate which might not be exactly rate * frame size. Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190830215910.31590-1-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-21ASoC: fsl_sai: Add support for imx8qmDaniel Baluta1-0/+7
SAI module on imx8qm features a register map similar with imx6 series (it doesn't have VERID and PARAM registers at the beginning of address spece). Also, it has one FIFO which can help up to 64 * 32 bit samples. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190814082911.665-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add support for imx7ulp/imx8mqDaniel Baluta1-0/+14
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM) at the beginning of register address space. On imx7ulp FIFOs can held up to 16 x 32 bit samples. On imx8mq FIFOs can held up to 128 x 32 bit samples. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-5-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add support for SAI new versionDaniel Baluta1-93/+135
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature. VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table: Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8. SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1]. In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf Signed-off-by: Mihai Serban <mihai.serban@nxp.com> [initial coding in the NXP internal tree] Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> [bugfixing and cleanups] Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> [adapted to linux-next] Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-4-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Update Tx/Rx channel enable maskDaniel Baluta1-2/+4
Tx channel enable (TCE) / Rx channel enable (RCE) bits enable corresponding data channel for Tx/Rx operation. Because SAI supports up the 8 channels TCE/RCE occupy up the 8 bits inside TCR3/RCR3 registers we need to extend the mask to reflect this. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-3-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add registers definition for multiple datalinesDaniel Baluta1-10/+66
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time. This patch adds definitions for all related data TX/RX registers: * TDR0..7, Transmit data register * TFR0..7, Transmit FIFO register * RDR0..7, Receive data register * RFR0..7, Receive FIFO register Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-02ASoC: Remove dev_err() usage after platform_get_irq()Stephen Boyd1-3/+1
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Cc: alsa-devel@alsa-project.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-50-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: mark regmap as fast_ioLucas Stach1-0/+1
The regmap is only ever used to access MMIO registers, so it's fair to say that register access is fast. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.kernel.org/r/20190717105156.15721-1-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: derive TX FIFO watermark from FIFO depthLucas Stach1-1/+3
The DMA request schould be triggered as soon as the FIFO has space for another burst. As different versions of the SAI block have different FIFO sizes, the watrmark level needs to be derived from version specific data. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Link: https://lore.kernel.org/r/20190717105635.18514-3-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: add of_match dataLucas Stach1-8/+14
New revisions of the SAI IP block have even more differences that need be taken into account by the driver. To avoid sprinking compatible checks all over the driver move the current differences into of_match_data. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190717105635.18514-2-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-31 15:04:50 +0000