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Add a pll mapping table for 19.2M in and 4.096M out.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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The maximum DMIC clock rate is 3.072 MHz for most DMIC. And it will get better
performance in higher clock rate. If we set maximum to 3 MHz in driver, we will
get a clock rate which is not even close to 3 MHz.
For example, if DMIC clock source is 24.576 MHz, the DMIC clock will be about
1.5 MHz in current code. But it will be 3.072 MHz with this patch.
Signed-off-by: John Lin <john.lin@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Few codecs will meet no DMIC clock output issue when select a divided
number which is divisible by 3. To prevent this issue, the patch ignore
the numbers when calculating the DMIC clock divider.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Existing implementation checks all divider values and tracks
'red' proximity value for the frequency.
But as divider array is monotonically increasing the first
divider that gives DMIC rate in 3MHz range is the best one
we should use. No need for 'red' zone tracking.
Additionally make sure that DMIC frequency is higher 1MHz.
Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
Acked-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Currently, rl6231_pll_calc provide a working PLL parameters for
given freq_in and freq_out. However, in some cases it is not the
perfect parameter. For example if freq_in = 19200000 and freq_out
= 24576000, the calculated parameter will gengrate 24.5647 MHz
which is not exactly the same as what we need. But the PLL can
output 24.576 MHz as exactly what we expect if we set the best
PLL parameter.
To improve it, we put the best match parameters in a preset table.
We can search the preset table first, if there is no preset parameter
for the given freq_in and freq_out, we can still calculate a working
PLL parameter.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The patch adds the function "get_clk_info" to RL6231 shared support.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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support
The patch adds the function of the PLL clock calculation to RL6231 shared
support.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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RT5651
The patch adds the RL6231 class device shared support for RT5640, RT5645 and
RT5651. The function of the DMIC clock calculation can be shared by RL6231
shared support.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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