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2022-04-22dt-bindings: clk: mpfs: add defines for two new clocksConor Dooley1-1/+4
The RTC reference and MSSPLL were previously not documented or defined, as they were unused. Add their defines to the PolarFire SoC header. Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-6-conor.dooley@microchip.com Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-01Merge tag 'rtc-5.18' of ↵Linus Torvalds1-0/+10
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux Pull RTC updates from Alexandre Belloni: "The bulk of the patches are about replacing the uie_unsupported struct rtc_device member by a feature bit. Subsystem: - remove uie_unsupported, all users have been converted to clear RTC_FEATURE_UPDATE_INTERRUPT and provide a reason - RTCs with an alarm with a resolution of a minute are now letting the core handle rounding down the alarm time - fix use-after-free on device removal New driver: - OP-TEE RTC PTA Drivers: - sun6i: Add H616 support - cmos: Fix the AltCentury for AMD platforms - spear: set range" * tag 'rtc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (56 commits) rtc: check if __rtc_read_time was successful rtc: gamecube: Fix refcount leak in gamecube_rtc_read_offset_from_sram rtc: mc146818-lib: Fix the AltCentury for AMD platforms rtc: optee: add RTC driver for OP-TEE RTC PTA rtc: pm8xxx: Return -ENODEV if set_time disallowed rtc: pm8xxx: Attach wake irq to device clk: sunxi-ng: sun6i-rtc: include clk/sunxi-ng.h rtc: remove uie_unsupported rtc: xgene: stop using uie_unsupported rtc: hym8563: switch to RTC_FEATURE_UPDATE_INTERRUPT rtc: hym8563: let the core handle the alarm resolution rtc: hym8563: switch to devm_rtc_allocate_device rtc: efi: switch to RTC_FEATURE_UPDATE_INTERRUPT rtc: efi: switch to devm_rtc_allocate_device rtc: add new RTC_FEATURE_ALARM_WAKEUP_ONLY feature rtc: spear: fix spear_rtc_read_time rtc: spear: drop uie_unsupported rtc: spear: set range rtc: spear: switch to devm_rtc_allocate_device rtc: pcf8563: switch to RTC_FEATURE_UPDATE_INTERRUPT ...
2022-03-30Merge tag 'clk-for-linus' of ↵Linus Torvalds17-373/+513
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...
2022-03-29Merge branches 'clk-sifive' and 'clk-visconti' into clk-nextStephen Boyd2-13/+13
* clk-sifive: clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being * clk-visconti: clk: visconti: prevent array overflow in visconti_clk_register_gates()
2022-03-29Merge branches 'clk-range', 'clk-uniphier', 'clk-apple' and 'clk-qcom' into ↵Stephen Boyd7-1/+171
clk-next - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range - Support for NCO blocks on Apple SoCs * clk-range: clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate clk: bcm: rpi: Run some clocks at the minimum rate allowed clk: bcm: rpi: Set a default minimum rate clk: bcm: rpi: Add variant structure clk: Add clk_drop_range clk: Always set the rate on clk_set_range_rate clk: Use clamp instead of open-coding our own clk: Always clamp the rounded rate clk: Enforce that disjoints limits are invalid clk: Introduce Kunit Tests for the framework clk: Fix clk_hw_get_clk() when dev is NULL * clk-uniphier: clk: uniphier: Fix fixed-rate initialization * clk-apple: clk: clk-apple-nco: Allow and fix module building MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE clk: clk-apple-nco: Add driver for Apple NCO dt-bindings: clock: Add Apple NCO * clk-qcom: (61 commits) clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops ...
2022-03-29Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' ↵Stephen Boyd4-359/+41
into clk-next - Audio clks on StarFive JH7100 RISC-V SoC - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments * clk-starfive: clk: starfive: Add JH7100 audio clock driver clk: starfive: jh7100: Support more clock types clk: starfive: jh7100: Make hw clock implementation reusable dt-bindings: clock: Add starfive,jh7100-audclk bindings dt-bindings: clock: Add JH7100 audio clock definitions clk: starfive: jh7100: Handle audio_div clock properly clk: starfive: jh7100: Don't round divisor up twice * clk-ti: clk: ti: Drop legacy compatibility clocks for dra7 clk: ti: Drop legacy compatibility clocks for am4 clk: ti: Drop legacy compatibility clocks for am3 clk: ti: Update component clocks to use ti_dt_clk_name() clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name() clk: ti: Add ti_dt_clk_name() helper to use clock-output-names clk: ti: Use clock-output-names for clkctrl clk: ti: Add ti_find_clock_provider() to use clock-output-names clk: ti: Optionally parse IO address from parent clock node clk: ti: Preserve node in ti_dt_clocks_register() clk: ti: Constify clkctrl_name * clk-terminate: clk: actions: Make sentinel elements more obvious clk: clps711x: Terminate clk_div_table with sentinel element clk: hisilicon: Terminate clk_div_table with sentinel element clk: loongson1: Terminate clk_div_table with sentinel element clk: actions: Terminate clk_div_table with sentinel element * clk-cleanup: clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments clk: COMMON_CLK_LAN966X should depend on SOC_LAN966 clk: Use of_device_get_match_data() clk: bcm2835: Remove unused variable clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver clk: cleanup comments clk: socfpga: cleanup spdx tags
2022-03-29Merge branches 'clk-mvebu', 'clk-const', 'clk-imx' and 'clk-rockchip' into ↵Stephen Boyd2-0/+273
clk-next - Mark mux table as const in clk-mux - Make the all_lists array const * clk-mvebu: clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it * clk-const: clk: Mark clk_core_evict_parent_cache_subtree() 'target' const clk: Mark 'all_lists' as const clk: pistachio: Declare mux table as const u32[] clk: qcom: Declare mux table as const u32[] clk: mmp: Declare mux tables as const u32[] clk: hisilicon: Remove unnecessary cast of mux table to u32 * clk: mux: Declare u32 *table parameter as const clk: nxp: Declare mux table parameter as const u32 * clk: nxp: Remove unused variable * clk-imx: (28 commits) dt-bindings: clock: drop useless consumer example clk: imx: Select MXC_CLK for i.MX93 clock driver clk: imx: remove redundant re-assignment of pll->base MAINTAINERS: clk: imx: add git tree and dt-bindings files clk: imx: pll14xx: Support dynamic rates clk: imx: pll14xx: Add pr_fmt clk: imx: pll14xx: explicitly return lowest rate clk: imx: pll14xx: name variables after usage clk: imx: pll14xx: consolidate rate calculation clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP clk: imx: pll14xx: Drop wrong shifting clk: imx: pll14xx: Use register defines consistently clk: imx8mp: remove SYS PLL 1/2 clock gates clk: imx8mn: remove SYS PLL 1/2 clock gates clk: imx8mm: remove SYS PLL 1/2 clock gates clk: imx: add i.MX93 clk clk: imx: support fracn gppll clk: imx: add i.MX93 composite clk dt-bindings: clock: add i.MX93 clock definition dt-bindings: clock: Add imx93 clock support ... * clk-rockchip: clk: rockchip: re-add rational best approximation algorithm to the fractional divider clk/rockchip: Use of_device_get_match_data() clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 clk: rockchip: Add more PLL rates for rk3568
2022-03-29Merge branches 'clk-xilinx', 'clk-kunit', 'clk-cs2000' and 'clk-renesas' ↵Stephen Boyd2-0/+243
into clk-next - Kunit tests for clk-gate implementation - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode * clk-xilinx: clk: zynqmp: replace warn_once with pr_debug for failed clock ops * clk-kunit: clk: gate: Add some kunit test suites * clk-cs2000: clk: cs2000-cp: convert driver to regmap clk: cs2000-cp: freeze config during register fiddling clk: cs2000-cp: make clock skip setting configurable clk: cs2000-cp: add support for dynamic mode clk: cs2000-cp: Make aux output function controllable dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag dt-bindings: clock: cs2000-cp: document aux-output-source dt-bindings: clock: convert cs2000-cp bindings to yaml * clk-renesas: dt-bindings: clock: renesas: Make example 'clocks' parsable clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: renesas: r8a779f0: Add PFC clock clk: renesas: r8a779f0: Add I2C clocks clk: renesas: r8a779f0: Add WDT clock clk: renesas: r8a779f0: Fix RSW2 clock divider clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC dt-bindings: clock: renesas: Document RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions clk: renesas: r8a779a0: Add CANFD module clock clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 clk: renesas: r8a7799[05]: Add MLP clocks clk: renesas: r8a779f0: Add SYS-DMAC clocks
2022-03-29Merge branches 'clk-microchip', 'clk-si', 'clk-mtk', 'clk-at91' and 'clk-st' ↵Stephen Boyd2-0/+47
into clk-next - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code * clk-microchip: clk: microchip: Add driver for Microchip PolarFire SoC dt-bindings: clk: microchip: Add Microchip PolarFire host binding * clk-si: clk-si5341: replace snprintf in show functions with sysfs_emit clk: si5341: fix reported clk_rate when output divider is 2 * clk-mtk: (32 commits) clk: mediatek: Warn if clk IDs are duplicated clk: mediatek: mt8195: Implement remove functions clk: mediatek: mt8195: Implement error handling in probe functions clk: mediatek: mt8195: Hook up mtk_clk_simple_remove() clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path clk: mediatek: mtk: Implement error handling in register APIs clk: mediatek: pll: Implement error handling in register API clk: mediatek: mux: Implement error handling in register API clk: mediatek: mux: Reverse check for existing clk to reduce nesting level clk: mediatek: gate: Implement error handling in register API clk: mediatek: cpumux: Implement error handling in register API clk: mediatek: mtk: Clean up included headers clk: mediatek: Add mtk_clk_simple_remove() clk: mediatek: Implement mtk_clk_unregister_composites() API clk: mediatek: Implement mtk_clk_unregister_divider_clks() API clk: mediatek: Implement mtk_clk_unregister_factors() API clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API clk: mediatek: pll: Clean up included headers clk: mediatek: pll: Implement unregister API clk: mediatek: pll: Split definitions into separate header file ... * clk-at91: clk: at91: clk-master: remove dead code clk: at91: sama7g5: fix parents of PDMCs' GCLK clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT * clk-st: clk: stm32mp1: Add parent_data to ETHRX clock clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock
2022-03-26Merge tag 'devicetree-for-5.18' of ↵Linus Torvalds9-14/+13
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Add Krzysztof Kozlowski as co-maintainer for DT bindings providing much needed help. - DT schema validation now takes DTB files as input rather than intermediate YAML files. This decouples the validation from the source level syntax information. There's a bunch of schema fixes as a result of switching to DTB based validation which exposed some errors and incomplete schemas and examples. - Kbuild improvements to explicitly warn users running 'make dt_binding_check' on missing yamllint - Expand DT_SCHEMA_FILES kbuild variable to take just a partial filename or path instead of the full path to 1 file. - Convert various bindings to schema format: mscc,vsc7514-switch, multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma, msm/mdp4, rda,8810pl-uart - New schemas for u-boot environment variable partition, TI clksel - New compatible strings for Renesas RZ/V2L SoC - Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated HiSilicon - Add/fix schemas for QEMU Arm 'virt' machine - Drop unused of_alias_get_alias_list() function - Add a script to check DT unittest EXPECT message output. Pass messages also now print by default at PR_INFO level to help test automation. * tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (96 commits) dt-bindings: kbuild: Make DT_SCHEMA_LINT a recursive variable dt-bindings: nvmem: add U-Boot environment variables binding dt-bindings: ufs: qcom: Add SM6350 compatible string dt-bindings: dmaengine: sifive,fu540-c000: include generic schema dt-bindings: gpio: pca95xx: drop useless consumer example Revert "of: base: Introduce of_alias_get_alias_list() to check alias IDs" dt-bindings: virtio,mmio: Allow setting devices 'dma-coherent' dt-bindings: gnss: Add two more chips dt-bindings: gnss: Rewrite sirfstar binding in YAML dt-bindings: gnss: Modify u-blox to use common bindings dt-bindings: gnss: Rewrite common bindings in YAML dt-bindings: ata: ahci-platform: Add rk3568-dwc-ahci compatible dt-bindings: ata: ahci-platform: Add power-domains property dt-bindings: ata: ahci-platform: Convert DT bindings to yaml dt-bindings: kbuild: Use DTB files for validation dt-bindings: kbuild: Pass DT_SCHEMA_FILES to dt-validate dt-bindings: Add QEMU virt machine compatible dt-bindings: arm: Convert QEMU fw-cfg to DT schema dt-bindings: i2c: at91: Add SAMA7G5 compatible strings list dt-bindings: i2c: convert i2c-at91 to json-schema ...
2022-03-25Merge tag 'riscv-for-linus-5.18-mw0' of ↵Linus Torvalds1-0/+45
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
2022-03-23Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds4-2/+364
Pull ARM devicetree updates from Arnd Bergmann: "After a somewhat quiet 5.17 release, the size of the DT changes is a bit larger again. There are nine new SoC that get added, all of them related to existing platforms: - Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB - Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G tablet - Microchip Lan966 networking SoC and it evaluation board - Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus 5X and Fairphone FP3 phones - Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along with their evaluation boards - Samsung Exynos 850 phone SoC and reference board - Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone - Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived from the Samsung Exynos family. - TI K3/AM62 SoC and reference board Support for additional functionality in existing dts files is added all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91, Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and Broadcom. Samsung has a rework for its pinctrl schema that is a bit tricky and requires driver changes to be included here. A few more platforms only have smaller cleanups and DT Schema fixes, this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno. The new machines are really too many to list, but I'll do it anyway: Allwinner: - A20-Marsboard development board Amlogic: - Amediatek X96-AIR (Amlogic S905X3) - CYX A95XF3-AIR (Amlogic S905X3) - Haochuangy H96-Max (Amlogic S905X3) - Amlogic AQ222 (Amlogic S4) - OSMC Vero 4K+ (Amlogic S905D) Arm Juno: - Separate DT depending on SCMI firmware version Aspeed: - Quanta S6Q BMC (AST2600) - ASRock ROMED8HM3 (AST2500) Broadcom: - Raspberry Pi Zero 2 W Marvell MVEBU/Armada: - Ctera C200 V1 NAS (kirkwood) - Ctera C200 V2 NAS (armada-370) Mstar: - DongShanPiOne, a low-end embedded board - Miyoo Mini handheld game console NXP i.MX: - Numerous i.MX8M Mini based boards in even more variations, but none based on other SoCs this time: Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and Gateworks GW7903 Qualcomm: - Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3) - SHIFT6mq phone (Snapdragon 845) - Samsung Galaxy Book2 (Snapdragon 850) - Snapdragon 8 Gen 1 Hardware Development Kit TI OMAP: - SanCloud BeagleBone Enhanced WiFi Rockchip: - Pine64 PineNote ereader tablet (rk356x) - Bananapi-R2-Pro (rk356x) STM32: - emtrion emSBS-Argon embedded board (stm32mp157c)" * tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits) arm64: dts: n5x: drop invalid property and fix edac node name arm64: dts: fsd: Add the MCT support arm64: dts: stingray: Fix spi clock name arm64: dts: ns2: Fix spi clock name ARM: dts: rockchip: Update regulator name for PX3 ARM: dts: rockchip: Add #clock-cells value for rk805 arm64: dts: rockchip: Add #clock-cells value for rk805 arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808 arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly ARM: dts: at91: sama7g5: Add NAND support ARM: dts: at91: sama7g5: add eic node ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15 arm64: dts: lg: align pl330 node name with dtschema arm64: dts: lg: add dma-cells to pl330 node arm64: dts: juno: align pl330 node name with dtschema arm64: dts: broadcom: Fix sata nodename arm64: dts: n5x: add sdr edac support arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node dt-bindings: usb: dwc2: add disable-over-current ...
2022-03-23Merge tag 'arm-drivers-5.18' of ↵Linus Torvalds1-0/+150
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM driver updates from Arnd Bergmann: "There are a few separately maintained driver subsystems that we merge through the SoC tree, notable changes are: - Memory controller updates, mainly for Tegra and Mediatek SoCs, and clarifications for the memory controller DT bindings - SCMI firmware interface updates, in particular a new transport based on OPTEE and support for atomic operations. - Cleanups to the TEE subsystem, refactoring its memory management For SoC specific drivers without a separate subsystem, changes include - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP Layerscape SoCs. - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L, and Qualcomm SM8450. - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older NVIDIA Tegra chips" * tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits) ARM: spear: fix typos in comments soc/microchip: fix invalid free in mpfs_sys_controller_delete soc: s4: Add support for power domains controller dt-bindings: power: add Amlogic s4 power domains bindings ARM: at91: add support in soc driver for new SAMA5D29 soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC memory: emif: check the pointer temp in get_device_details() memory: emif: Add check for setup_interrupts dt-bindings: arm: mediatek: mmsys: add support for MT8186 dt-bindings: mediatek: add compatible for MT8186 pwrap soc: mediatek: pwrap: add pwrap driver for MT8186 SoC soc: mediatek: mmsys: add mmsys reset control for MT8186 soc: mediatek: mtk-infracfg: Disable ACP on MT8192 soc: ti: k3-socinfo: Add AM62x JTAG ID soc: mediatek: add MTK mutex support for MT8186 soc: mediatek: mmsys: add mt8186 mmsys routing table soc: mediatek: pm-domains: Add support for mt8186 dt-bindings: power: Add MT8186 power domains soc: mediatek: pm-domains: Add support for mt8195 ...
2022-03-15dt-bindings: change the macro name of prci in header files and exampleZong Li2-13/+13
We currently change the macro name for fu540 and fu740 by adding the prefix respectively, the dt-bindings should be modified as well. Signed-off-by: Zong Li <zong.li@sifive.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/f9284873c2993a9952d9fe4f8dd5e89f20daab75.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-15clk: ti: Drop legacy compatibility clocks for dra7Tony Lindgren1-168/+0
We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Depends-on: 31aa7056bbec ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl") Depends-on: 9206a3af4fc0 ("clk: ti: Move dra7 clock devices out of the legacy section") Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220203085618.16043-4-tony@atomide.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-15clk: ti: Drop legacy compatibility clocks for am4Tony Lindgren1-98/+0
We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220203085618.16043-3-tony@atomide.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-15clk: ti: Drop legacy compatibility clocks for am3Tony Lindgren1-93/+0
We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220203085618.16043-2-tony@atomide.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-10dt-bindings: clock: Add JH7100 audio clock definitionsEmil Renner Berthing1-0/+41
Add all clock outputs for the StarFive JH7100 audio clock generator. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220126173953.1016706-4-kernel@esmil.dk Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-10dt-bindings: clk: cleanup commentsTom Rix9-14/+13
For spdx, first line /* */ for *.h, change tab to space Replacements devider to divider Comunications to Communications periphrals to peripherals supportted to supported wich to which Documentatoin to Documentation Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220309222302.1114561-1-trix@redhat.com
2022-03-09dt-bindings: clock: add QCOM SM6125 display clock bindingsMartin Botka1-0/+41
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-3-marijn.suijten@somainline.org
2022-03-09clk: qcom: gcc: Add emac GDSC support for SM8150Bhupesh Sharma1-0/+1
Add the EMAC GDSC defines and driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303084824.284946-4-bhupesh.sharma@linaro.org
2022-03-09clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150Bhupesh Sharma1-0/+2
Add the UFS_CARD and UFS_PHY GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303082140.240745-2-bhupesh.sharma@linaro.org
2022-03-09clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150Bhupesh Sharma1-0/+2
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org
2022-03-08dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocksKonrad Dybcio1-0/+2
Add the missing clock definitions. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226214126.21209-1-konrad.dybcio@somainline.org
2022-03-08dt-bindings: clock: add ipq8064 ce5 clk defineAnsuel Smith1-1/+4
Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Define CE5_SRC is not used so it's OK to change and we align it to the QSDK naming. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com
2022-03-08dt-bindings: clock: add SM6350 QCOM Graphics clock bindingsKonrad Dybcio1-0/+37
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6350 SoCs. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-3-konrad.dybcio@somainline.org
2022-03-08dt-bindings: clock: add QCOM SM6350 display clock bindingsKonrad Dybcio1-0/+48
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-1-konrad.dybcio@somainline.org
2022-03-08Merge tag 'at91-dt-5.18-2' of ↵Arnd Bergmann1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 DT #2 for 5.18: - Align one sam9x60ek regulator with reality at vdd_1v15 - Clean sama7g5 i2c nodes - Add EIC and NAND nodes to sama7g5 * tag 'at91-dt-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sama7g5: Add NAND support ARM: dts: at91: sama7g5: add eic node ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15 Link: https://lore.kernel.org/r/20220304160036.27392-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-04dt-bindings: clock: add i.MX93 clock definitionPeng Fan1-0/+201
Add i.MX93 clock definition Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04ARM: dts: at91: sama7g5: Add NAND supportTudor Ambarus1-0/+1
Add NAND support. The sama7g5's SMC IP is the same as sama5d2's with a slightly change: it provides a synchronous clock output (SMC clock) that is dedicated to FPGA usage. Since this doesn't interfere with the SMC NAND configuration, thus code will not be added in the current nand driver to address the FPGA usage, use the sama5d2's compatible and choose not to introduce dedicated compatibles for sama7g5. Tested with Micron MT29F4G08ABAEAWP NAND flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> [nicolas.ferre@microchip.com: add the definition of PMC_MCK1 in include/dt-bindings/clock/at91.h from another patch] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220111130556.905978-1-tudor.ambarus@microchip.com
2022-02-28Merge tag 'tegra-for-5.18-dt-bindings' of ↵Arnd Bergmann1-2/+133
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.18-rc1 This contains additions to various DT bindings includes (such as clocks, resets, power domains, memory controller clients and SMMU stream IDs) for Tegra234. * tag 'tegra-for-5.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add Tegra234 PCIe memory dt-bindings: power: Add Tegra234 PCIe power domains dt-bindings: Add Tegra234 PCIe clocks and resets dt-bindings: Document Tegra234 HDA support dt-bindings: Add HDA support for Tegra234 dt-bindings: Add Tegra234 APE support dt-bindings: Add headers for Tegra234 PWM dt-bindings: Add headers for Tegra234 I2C Link: https://lore.kernel.org/r/20220225164741.1064416-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'renesas-arm-dt-for-v5.18-tag2' of ↵Arnd Bergmann1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.18 (take two) - Document the use of the renesas-soc IRC channel, - Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: dts: renesas: Align GPIO hog names with dtschema arm64: dts: renesas: Align GPIO hog names with dtschema arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout ARM: dts: r9a06g032: Add the watchdog nodes dt-bindings: clock: r9a06g032: Add the definition of the watchdog clock arm64: dts: renesas: spider-cpu: Enable watchdog timer arm64: dts: renesas: r8a779f0: Add RWDT node MAINTAINERS: Specify IRC channel for Renesas ARM64 port MAINTAINERS: Specify IRC channel for Renesas ARM32 port arm64: dts: renesas: ulcb-kf: fix wrong comment Link: https://lore.kernel.org/r/cover.1645784466.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-25Merge tag 'renesas-arm-dt-for-v5.18-tag1' of ↵Arnd Bergmann1-0/+229
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.18 - External interrupt (INTC-EX) support for the R-Car V3U SoC, - Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and RZ/V2L SMARC EVK development boards, - Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle and Condor development boards, - NAND support for the RZ/N1D SoC, - DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC, - LVDS support for the R-Car M3-W+ SoC, - HDMI output and 9-axis sensor support for the Kingfisher (ULCB extension) board, - MAX96712 GMSL serializer support for the Falcon development board, - MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3 SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits) arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings arm64: dts: renesas: rzg2l-smarc: Add common dtsi file arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound arm64: dts: renesas: rcar-gen3: Add MOST devices arm64: dts: renesas: Miscellaneous whitespace fixes arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712 arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device arm64: dts: renesas: ulcb-kf: Add KF HDMI output arm64: dts: renesas: r8a77961: Add lvds0 device node arm64: dts: renesas: r8a779f0: Add sys-dmac nodes ARM: dts: r9a06g032: Describe the NAND controller arm64: dts: renesas: Add GMSL cameras .dtsi ... Link: https://lore.kernel.org/r/cover.1644587200.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-24dt-bindings: Add Tegra234 PCIe clocks and resetsVidya Sagar1-0/+22
Add the clocks and resets used by the PCIe hardware found on Tegra234 SoCs. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24dt-bindings: Add HDA support for Tegra234Mohan Kumar1-0/+4
Add hda clocks, memory ,power and reset binding entries for Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24dt-bindings: clock: r9a06g032: Add the definition of the watchdog clockJean-Jacques Hiblot1-0/+1
This clock is actually the REF_SYNC_D8 clock. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220221095032.95054-2-jjhiblot@traphandler.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-17dt-bindings: Add Tegra234 APE supportSameer Pujar1-1/+73
Add clocks, power-domain and memory bindings to support APE subsystem on Tegra234. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-15dt-bindings: rtc: sun6i: Add H616, R329, and D1 supportSamuel Holland1-0/+10
These new RTC variants all have a single alarm, like the R40 variant. For the new SoCs, start requiring a complete list of input clocks. The H616 has three required clocks. The R329 also has three required clocks (but one is different), plus an optional crystal oscillator input. The D1 RTC is identical to the one in the R329. And since these new SoCs will have a well-defined output clock order as well, they do not need the clock-output-names property. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20220203021736.13434-3-samuel@sholland.org
2022-02-10dt-bindings: clock: Add qualcomm QCM2290 DISPCC bindingsLoic Poulain1-0/+34
Add device tree bindings for display clock controller on QCM2290 SoCs. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644432308-21099-1-git-send-email-loic.poulain@linaro.org
2022-02-07Merge tag 'omap-for-v5.17/fixes-for-merge-window-signed' of ↵Arnd Bergmann1-7/+7
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Fixes for omaps A series of fixes for omap variants for minor issues, and a fix for a timer regression for some omap3 beagleboard versions. The timer fix needs to patch both the dts and the timer code because otherwise the timer quirk handling for old dtbs will prevent the dts fix from working. The other changes are for issues found by automated analysis, a macasp typo fix, and two cosmetic fixes for clocks. * tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Don't use legacy clock defines for dra7 clkctrl clk: ti: Move dra7 clock devices out of the legacy section ARM: dts: Fix timer regression for beagleboard revision c ARM: dts: am335x-wega: Fix typo in mcasp property rx-num-evt ARM: OMAP2+: adjust the location of put_device() call in omapdss_init_of ARM: OMAP2+: hwmod: Add of_node_put() before break Link: https://lore.kernel.org/r/pull-1641801310-149268@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-03dt-bindings: Add headers for Tegra234 PWMAkhil R1-0/+16
Add dt-bindings header files for PWM of Tegra234 Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-03dt-bindings: Add headers for Tegra234 I2CAkhil R1-1/+18
Add dt-bindings header files for I2C controllers for Tegra234 Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-02dt-bindings: clock: Add R9A07G054 CPG Clock and Reset DefinitionsBiju Das1-0/+229
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev. 1.00, Nov. 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220126211003.6675-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-29dt-bindings: imx: Add clock binding for i.MXRT1050Giulio Benetti1-0/+72
Add the clock binding doc for i.MXRT1050. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> [Jesse: added clocks from IMXRT1050_CLK_IPG_PDOF to IMXRT1050_CLK_DMA_MUX and moved IMXRT1050_CLK_END on] Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220111215415.2075257-4-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-01-26dt-bindings: clock: Add bindings definitions for FSD CMU blocksAlim Akhtar1-0/+150
Clock controller driver of FSD platform is designed to have separate instances for each particular CMU. So clock IDs in this bindings header also start from 1 for each CMU block. Cc: linux-fsd@tesla.com Reported-by: kernel test robot <lkp@intel.com> [robot: reported missing #endif] Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20220124141644.71052-3-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2022-01-25dt-bindings: clock: cs2000-cp: document aux-output-sourceDaniel Mack1-0/+14
This new optional property can be used to control the function of the auxiliary output pin. Introduce a new dt-bindings include file that contains the numerical values. Signed-off-by: Daniel Mack <daniel@zonque.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220125093336.226787-3-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus1-0/+1
MCK1 feeds the External Bus Interface (EBI). EBI's clock rate is used to translate EBI's timmings to SMC timings, thus we need to handle MCK1 in the EBI driver. Allow MCK1 to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220111125310.902856-1-tudor.ambarus@microchip.com Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24clk: at91: allow setting PMC_AUDIOPINCK clock parents via DTZixun LI1-0/+1
Make AUDIOPINCK accessible via phandle to select it as peripheral clock parent using assigned-clock-parents in DT where available. Signed-off-by: Zixun LI <admin@hifiphile.com> Reviewed-by: Claudiu Beznea <Claudiu.Beznea@microchip.com> Link: https://lore.kernel.org/r/20220111142051.37957-1-admin@hifiphile.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-24dt-bindings: clk: microchip: Add Microchip PolarFire host bindingDaire McNamara1-0/+45
Add device tree bindings for the Microchip PolarFire system clock controller Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211216140022.16146-2-conor.dooley@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds13-5/+975
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have a couple patches in the framework core this time around but they're mostly minor cleanups and some debugfs stuff. The real work that's in here is the typical pile of clk driver updates and new SoC support. Per usual (or maybe just recent trends), Qualcomm gains a handful of SoC drivers additions and has the largest diffstat. After that there are quite a few updates to the Allwinner (sunxi) drivers to support modular drivers and Renesas is heavily updated to add more support for various clks. Overall it looks pretty normal. New Drivers: - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770 - MediaTek mt7986 SoC basic support - Clock and reset driver for Toshiba Visconti SoCs - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) - Allwinner D1 clks - Lan966x Generic Clock Controller driver and associated DT bindings - Qualcomm SDX65, SM8450, and MSM8976 GCC clks - Qualcomm SDX65 and SM8450 RPMh clks Updates: - Set suppress_bind_attrs to true for i.MX8ULP driver - Switch from do_div to div64_ul for throughout all i.MX drivers - Fix imx8mn_clko1_sels for i.MX8MN - Remove unused IPG_AUDIO_ROOT from i.MX8MP - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver - Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - Refactoring of the CPU clocks registration to use common interface - An update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - Prep for runtime PM and generic power domains on Tegra - Support modular Allwinner clk drivers via platform bus - Lan966x clock driver extended to support clock gating - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and thermal (TSU) clocks and resets on Renesas RZ/G2L - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock drivers, and in the Renesas SDHI driver - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Add clk-provider.h to various Qualcomm clk drivers - devm version of clk_hw_register_gate() - kerneldoc fixes in a couple drivers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits) clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks clk: bm1880: remove kfrees on static allocations clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent clk: Enable/Disable runtime PM for clk_summary MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver ...
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-20 04:02:38 +0000