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2019-08-17net: phy: remove genphy_config_initHeiner Kallweit1-51/+0
Now that all users have been removed we can remove genphy_config_init. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: phy: remove calls to genphy_config_initHeiner Kallweit10-33/+9
Supported PHY features are either auto-detected or explicitly set. In both cases calling genphy_config_init isn't needed. All that genphy_config_init does is removing features that are set as supported but can't be auto-detected. Basically it duplicates the code in genphy_read_abilities. Therefore remove such calls from all PHY drivers. v2: - remove call also from new adin PHY driver v3: - pass NULL as config_init function pointer for dp83848 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16ipvlan: set hw_enc_features like macvlanBill Sommerfeld1-0/+1
Allow encapsulated packets sent to tunnels layered over ipvlan to use offloads rather than forcing SW fallbacks. Since commit f21e5077010acda73a60 ("macvlan: add offload features for encapsulation"), macvlan has set dev->hw_enc_features to include everything in dev->features; do likewise in ipvlan. Signed-off-by: Bill Sommerfeld <wsommerfeld@google.com> Acked-by: Mahesh Bandewar <maheshb@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: dsa: mv88e6xxx: check for mode change in port_setup_macMarek Behún3-1/+42
The mv88e6xxx_port_setup_mac checks if the requested MAC settings are different from the current ones, and if not, does nothing (since chaning them requires putting the link down). In this check it only looks if the triplet [link, speed, duplex] is being changed. This patch adds support to also check if the mode parameter (of type phy_interface_t) is requested to be changed. The current mode is computed by the ->port_link_state() method, and if it is different from PHY_INTERFACE_MODE_NA, we check for equality with the requested mode. In the implementations of the mv88e6250_port_link_state() method we set the current mode to PHY_INTERFACE_MODE_NA - so the code does not check for mode change on 6250. In the mv88e6352_port_link_state() method, we use the cached cmode of the port to determine the mode as phy_interface_t (and if it is not enough, eg. for RGMII, we also look at the port control register for RX/TX timings). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add ethtool get_stats supportAlexandru Ardelean1-0/+128
This change implements retrieving all the error counters from the PHY. The counters require that the RxErrCnt register (0x0014) be read first, after which copies of the counters are latched into the registers. This ensures that all registers read after RxErrCnt are synchronized at the moment that they are read. The counter values need to be accumulated by the driver, as each time that RxErrCnt is read, the values that are latched are the ones that have incremented from the last read. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: implement downshift configuration via phy-tunableAlexandru Ardelean1-0/+86
Down-speed auto-negotiation may not always be enabled, in which case the PHY won't down-shift to 100 or 10 during auto-negotiation. This change enables downshift and configures the number of retries to default 4 (which is also in the datasheet The downshift control mechanism can also be controlled via the phy-tunable interface (ETHTOOL_PHY_DOWNSHIFT control). The change has been adapted from the Aquantia PHY driver. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: implement PHY subsystem software resetAlexandru Ardelean1-0/+26
The ADIN PHYs supports 4 types of reset: 1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg 2. Reset via GPIO 3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs 4. Reset via reg GeSftRst (0xff0c) & request new pin configs Resets 2, 3 & 4 are almost identical, with the exception that the crystal oscillator is available during reset for 2. This change implements subsystem software reset via the GeSftRst and reloading the previous pin configuration (so reset number 3). This will also reset the PHY core regs (similar to reset 1). Since writing bit 1 to reg GeSftRst is self-clearing, the only thing that can be done, is to write to that register, wait a specific amount of time (10 milliseconds should be enough) and try to read back and check if there are no errors on read. A busy-wait-read won't work well, and may sometimes work or not work. In case phylib is configured to also do a reset via GPIO, the ADIN PHY may be reset twice when the PHY device registers, but that isn't a problem, since it's being done on boot (or PHY device register). Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add EEE translation layer from Clause 45 to Clause 22Alexandru Ardelean1-2/+66
The ADIN1200 & ADIN1300 PHYs support EEE by using standard Clause 45 access to access MMD registers for EEE. The EEE register addresses (when using Clause 22) are available at different addresses (than Clause 45), and since accessing these regs (via Clause 22) needs a special mechanism, a translation table is required to convert these addresses. For Clause 45, this is not needed since the driver will likely never use this access mode. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add support MDI/MDIX/Auto-MDI selectionAlexandru Ardelean1-4/+113
The ADIN PHYs support automatic MDI/MDIX negotiation. By default this is disabled, so this is enabled at `config_init`. This is controlled via the PHY Control 1 register. The supported modes are: 1. Manual MDI 2. Manual MDIX 3. Auto MDIX - prefer MDIX 4. Auto MDIX - prefer MDI The phydev mdix & mdix_ctrl fields include modes 3 & 4 into a single auto-mode. So, the default mode this driver enables is 4 when Auto-MDI mode is used. When detecting MDI/MDIX mode, a combination of the PHY Control 1 register and PHY Status 1 register is used to determine the correct MDI/MDIX mode. If Auto-MDI mode is not set, then the manual MDI/MDIX mode is returned. If Auto-MDI mode is set, then MDIX mode is returned differs from the preferred MDI/MDIX mode. This covers all cases where: 1. MDI preferred & Pair01Swapped == MDIX 2. MDIX preferred & Pair01Swapped == MDI 3. MDI preferred & ! Pair01Swapped == MDIX 4. MDIX preferred & ! Pair01Swapped == MDI The preferred MDI/MDIX mode is not configured via SW, but can be configured via HW pins. Note that the `Pair01Swapped` is the Green-Yellow physical pairs. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: make RMII fifo depth configurableAlexandru Ardelean1-0/+29
The FIFO depth can be configured for the RMII mode. This change adds support for doing this via device-tree (or ACPI). Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: make RGMII internal delays configurableAlexandru Ardelean1-0/+82
The internal delays for the RGMII are configurable for both RX & TX. This change adds support for configuring them via device-tree (or ACPI). Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: configure RGMII/RMII/MII modes on configAlexandru Ardelean1-1/+78
The ADIN1300 chip supports RGMII, RMII & MII modes. Default (if unconfigured) is RGMII. This change adds support for configuring these modes via the device registers. For RGMII with internal delays (modes RGMII_ID,RGMII_TXID, RGMII_RXID), the default delay is 2 ns. This can be configurable and will be done in a subsequent change. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add {write,read}_mmd hooksAlexandru Ardelean1-0/+34
Both ADIN1200 & ADIN1300 support Clause 45 access for some registers. The Extended Management Interface (EMI) registers are accessible via both Clause 45 (at register MDIO_MMD_VEND1) and using Clause 22. The Clause 22 access for MMD regs differs from the standard one defined by 802.3. The ADIN PHYs use registers ExtRegPtr (0x0010) and ExtRegData (0x0011) to access Clause 45 & EMI registers. The indirect access is done via the following mechanism (for both R/W): 1. Write the address of the register in the ExtRegPtr 2. Read/write the value of the register via reg ExtRegData This mechanism is needed to manage configuration of chip settings and to access EEE registers via Clause 22. Since Clause 45 access will likely never be used, it is not implemented via this hook. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add support for interruptsAlexandru Ardelean1-0/+36
This change hooks link-status-change interrupts to phylib. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: hook genphy_{suspend, resume} into the driverAlexandru Ardelean1-0/+4
The chip supports standard suspend/resume via BMCR reg. Hook these functions into the `adin` driver. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add support for Analog Devices PHYsAlexandru Ardelean3-0/+59
This change adds support for Analog Devices Industrial Ethernet PHYs. Particularly the PHYs this driver adds support for: * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit Ethernet PHY The 2 chips are register compatible with one another. The main difference being that ADIN1200 doesn't operate in gigabit mode. The chips can be operated by the Generic PHY driver as well via the standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the kernel as well. This assumes that configuration of the PHY has been done completely in HW, according to spec. Configuration can also be done via registers, which will be supported by this driver. Datasheets: https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: PTP Hardware Clock (PHC) supportAntoine Tenart3-13/+539
This patch adds support for PTP Hardware Clock (PHC) to the Ocelot switch for both PTP 1-step and 2-step modes. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: remove the frame_info cpuq memberAntoine Tenart2-2/+0
In struct frame_info, the cpuq member is never used. This cosmetic patch removes it from the structure, and from the parsing of the frame header as it's only set but never used. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: improve the frame header parsing readabilityAntoine Tenart1-11/+13
This cosmetic patch improves the frame header parsing readability by introducing a new macro to access and mask its fields. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: describe the PTP register rangeAntoine Tenart4-1/+70
This patch adds support for using the PTP register range, and adds a description of its registers. This bank is used when configuring PTP. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15qed: Add driver API for flashing the config attributes.Sudarsana Reddy Kalluru1-0/+68
The patch adds driver interface for reading the config attributes from user provided buffer, and updates these values on nvm config flash partition. This is basically an expansion of our existing ethtool -f implementation. The management FW has exposed an additional method of configuring some of the nvram options, and this makes use of that. This implementation will come into use when newer FW files which contain configuration directives employing this API will be provided to ethtool -f. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15qed: Add API for configuring NVM attributes.Sudarsana Reddy Kalluru3-0/+69
The patch adds API for configuring the NVM config attributes using Management FW (MFW) interfaces. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15Merge tag 'linux-can-next-for-5.4-20190814' of ↵David S. Miller5-166/+125
git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next Marc Kleine-Budde says: ==================== pull-request: can-next 2019-08-14 this is a pull request for net-next/master consisting of 41 patches. The first two patches are for the kvaser_pciefd driver: Christer Beskow removes unnecessary code in the kvaser_pciefd_pwm_stop() function, YueHaibing removes the unused including of <linux/version.h>. In the next patch YueHaibing also removes the unused including of <linux/version.h> in the f81601 driver. In the ti_hecc driver the next 6 patches are by me and fix checkpatch warnings. YueHaibing's patch removes an unused variable in the ti_hecc_mailbox_read() function. The next 6 patches all target the xilinx_can driver. Anssi Hannula's patch fixes a chip start failure with an invalid bus. The patch by Venkatesh Yadav Abbarapu skips an error message in case of a deferred probe. The 3 patches by Appana Durga Kedareswara rao fix the RX and TX path for CAN-FD frames. Srinivas Neeli's patch fixes the bit timing calculations for CAN-FD. The next 12 patches are by me and several checkpatch warnings in the af_can, raw and bcm components. Thomas Gleixner provides a patch for the bcm, which switches the timer to HRTIMER_MODE_SOFT and removes the hrtimer_tasklet. Then 6 more patches by me for the gw component, which fix checkpatch warnings, followed by 2 patches by Oliver Hartkopp to add CAN-FD support. The vcan driver gets 3 patches by me, fixing checkpatch warnings. And finally a patch by Andre Hartmann to fix typos in CAN's netlink header. ====================
2019-08-15netdevsim: implement support for devlink region and snapshotsJiri Pirko2-1/+63
Implement dummy region of size 32K and allow user to create snapshots or random data using debugfs file trigger. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15r8169: sync EEE handling for RTL8168h with vendor driverHeiner Kallweit1-1/+11
Sync EEE init for RTL8168h with vendor driver and add two writes to vendor-specific registers. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15r8169: use the generic EEE management functionsHeiner Kallweit1-148/+24
Now that the Realtek PHY driver maps the vendor-specific EEE registers to the standard MMD registers, we can remove all special handling and use the generic functions phy_ethtool_get/set_eee. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: phy: realtek: add support for EEE registers on integrated PHY'sHeiner Kallweit1-0/+43
EEE-related registers on newer integrated PHY's have the standard layout, but are accessible not via MMD but via vendor-specific registers. Emulating the standard MMD registers allows to use the generic functions for EEE control. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: phy: swphy: emulate register MII_ESTATUSHeiner Kallweit1-0/+8
When the genphy driver binds to a swphy it will call genphy_read_abilites that will try to read MII_ESTATUS if BMSR_ESTATEN is set in MII_BMSR. So far this would read the default value 0xffff and 1000FD and 1000HD are reported as supported just by chance. Better add explicit support for emulating MII_ESTATUS. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: phy: read MII_CTRL1000 in genphy_read_status only if neededHeiner Kallweit1-5/+6
Value of MII_CTRL1000 is needed only if LPA_1000MSFAIL is set. Therefore move reading this register. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-14net/mvpp2: Replace tasklet with softirq hrtimerThomas Gleixner2-38/+23
The tx_done_tasklet tasklet is used in invoke the hrtimer (mvpp2_hr_timer_cb) in softirq context. This can be also achieved without the tasklet but with HRTIMER_MODE_SOFT as hrtimer mode. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-14net: phy: realtek: add NBase-T PHY auto-detectionHeiner Kallweit1-5/+43
Realtek provided information on how the new NIC-integrated PHY's expose whether they support 2.5G/5G/10G. This allows to automatically differentiate 1Gbps and 2.5Gbps PHY's, and therefore allows to remove the fake PHY ID mechanism for RTL8125. So far RTL8125 supports 2.5Gbps only, but register layout for faster modes has been defined already, so let's use this information to be future-proof. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-14r8169: fix sporadic transmit timeout issueHeiner Kallweit1-0/+1
Holger reported sporadic transmit timeouts and it turned out that one path misses ringing the doorbell. Fix was suggested by Eric. Fixes: ef14358546b1 ("r8169: make use of xmit_more") Suggested-by: Eric Dumazet <edumazet@google.com> Tested-by: Holger Hoffstätte <holger@applied-asynchrony.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-13r8152: change rx_copybreak and rx_pending through ethtoolHayes Wang1-5/+86
Let the rx_copybreak and rx_pending could be modified by ethtool. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13r8152: support skb_add_rx_fragHayes Wang1-15/+105
Use skb_add_rx_frag() to reduce the memory copy for rx data. Use a new list of rx_used to store the rx buffer which couldn't be reused yet. Besides, the total number of rx buffer may be increased or decreased dynamically. And it is limited by RTL8152_MAX_RX_AGG. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13r8152: use alloc_pages for rx bufferHayes Wang1-20/+11
Replace kmalloc_node() with alloc_pages() for rx buffer. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13r8152: replace array with linking list for rx informationHayes Wang1-57/+125
The original method uses an array to store the rx information. The new one uses a list to link each rx structure. Then, it is possible to increase/decrease the number of rx structure dynamically. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13r8152: separate the rx buffer sizeHayes Wang1-4/+8
The different chips may accept different rx buffer sizes. The RTL8152 supports 16K bytes, and RTL8153 support 32K bytes. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13net: phy: let phy_speed_down/up support speeds >1GbpsHeiner Kallweit1-44/+16
So far phy_speed_down/up can be used up to 1Gbps only. Remove this restriction by using new helper __phy_speed_down. New member adv_old in struct phy_device is used by phy_speed_up to restore the advertised modes before calling phy_speed_down. Don't simply advertise what is supported because a user may have intentionally removed modes from advertisement. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13net: phy: add phy_speed_down_core and phy_resolve_min_speedHeiner Kallweit1-0/+28
phy_speed_down_core provides most of the functionality for phy_speed_down. It makes use of new helper phy_resolve_min_speed that is based on the sorting of the settings[] array. In certain cases it may be helpful to be able to exclude legacy half duplex modes, therefore prepare phy_resolve_min_speed() for it. v2: - rename __phy_speed_down to phy_speed_down_core Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13net: phy: add __set_linkmode_max_speedHeiner Kallweit1-2/+7
We will need the functionality of __set_linkmode_max_speed also for linkmode bitmaps other than phydev->supported. Therefore split it. v2: - remove unused parameter from __set_linkmode_max_speed Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13net: hns3: Make hclge_func_reset_sync_vf staticYueHaibing1-1/+1
Fix sparse warning: drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c:3190:5: warning: symbol 'hclge_func_reset_sync_vf' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
2019-08-13can: vcan: introduce pr_fmt and make use of itMarc Kleine-Budde1-2/+4
This patch introduces pr_fmt and makes use of it, also it converts a printk() to pr_info(). Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: vcan: remove unnecessary blank linesMarc Kleine-Budde1-2/+0
This patch removes unnecessary blank lines, so that checkpatch doesn't complain anymore. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: vcan: convert block comments to network style commentsMarc Kleine-Budde1-8/+3
This patch converts all block comments to network subsystem style block comments. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: xilinx_can: xcan_set_bittiming(): fix the data phase btr1 calculationSrinivas Neeli1-1/+1
While calculating bitrate for the data phase, the driver is using phase segment 1 of the arbitration phase instead of the data phase. Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames") Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: xilinx_can: xcan_rx_fifo_get_next_frame(): fix FSR register FL and RI ↵Appana Durga Kedareswara rao1-3/+10
mask values for canfd 2.0 For CANFD 2.0 IP configuration existing driver is using incorrect mask values for FSR register FL and RI fields. Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames") Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: xilinx_can: fix the data update logic for CANFD FD framesAppana Durga Kedareswara rao1-21/+8
commit c223da689324 ("can: xilinx_can: Add support for CANFD FD frames") is writing data to a wrong offset for FD frames. This patch fixes this issue. Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames") Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: xilinx_can: xcanfd_rx(): fix FSR register handling in the RX pathAppana Durga Kedareswara rao1-76/+63
After commit c223da689324 ("can: xilinx_can: Add support for CANFD FD frames") the driver is updating the FSR IRI index multiple times (i.e in xcanfd_rx() and xcan_rx_fifo_get_next_frame()), It should be updated once per RX packet. This patch fixes this issue, also this patch removes the unnecessary fsr register checks in xcanfd_rx() API. Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames") Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: xilinx_can: xcan_probe(): skip error message on deferred probeVenkatesh Yadav Abbarapu1-1/+2
When can clock is provided from the clock wizard, clock wizard driver may not be available when can driver probes resulting to the error message "Device clock not found error". As this error message is not very userful to the end user, skip printing it in the case of deferred probe. Fixes: b1201e44 ("can: xilinx CAN controller support") Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2019-08-13can: xilinx_can: xcan_chip_start(): fix failure with invalid busAnssi Hannula1-12/+1
Currently the xilinx_can xcan_chip_start() function, called from .ndo_open() and via CAN_MODE_START (bus-off restart), waits for the SR register to show the wanted operating state, with a 1 sec timeout. However, that register bit will only be set once the HW has observed 11 consecutive recessive bits (BusIdle) on the bus. If the bus will not see the 11 bits (e.g. it is stuck dominant), the function will timeout and return an error. If this was done as part of a scheduled restart from bus-off, the interface will stay in bus-off state forever even if the bus recovers later. According to M_CAN and FLEXCAN documentation they also wait for 11 consecutive recessive bits, but their drivers do not seem to wait for that. To make the behavior consistent, modify xilinx_can to also not wait for the synchronization to complete. The only way for users to know for sure that the bus has been joined successfully is to see successfully received or transmitted frames. That does not seem optimal, but it is consistent with other drivers and we should have a properly working restart-ms with xilinx_can. Tested on ZynqMP with Xilinx CAN-FD 1.0. Fixes: b1201e44f50b ("can: xilinx CAN controller support") Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi> Tested-by: Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>