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2020-04-29staging: rtl8723bs: remove mgmt_frame_register methodJohannes Berg1-24/+0
This was changed in cfg80211, so having it broke things, but there's no need to adjust since it's an empty implementation. Just remove it. Fixes: 6cd536fe62ef ("cfg80211: change internal management frame registration API") Signed-off-by: Johannes Berg <johannes.berg@intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20200428101400.ae19d651ec38.Ieb15844bb5ab93b3d7931d6561f42e3316ef8251@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2020-04-24mac80211_hwsim: indicate in IBSS that we have transmitted beaconsJohannes Berg1-0/+6
This is actually true because there's no functional beacon distribution and lets us get active scanning working - without it, mac80211 doesn't respond to probe requests. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20200326150855.554d1199b309.Id86fd36e3d88d2a75d6e0c6618fd93ce8fe84065@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2020-04-24mac80211: implement Operating Mode Notification extended NSS supportJohannes Berg1-3/+3
Somehow we missed this for a long time, but similar to the extended NSS support in VHT capabilities, we need to have this in Operating Mode notification. Implement it by * parsing the 160/80+80 bit there and setting the bandwidth appropriately * having callers of ieee80211_get_vht_max_nss() pass in the current max NSS value as received in the operating mode notification in order to modify it appropriately depending on the extended NSS bits. This updates all drivers that use it, i.e. only iwlwifi/mvm. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20200326150855.098483728cfa.I4e8c25d3288441759c2793247197229f0696a37d@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2020-04-24cfg80211: change internal management frame registration APIJohannes Berg4-76/+68
Almost all drivers below cfg80211 get the API wrong (except for cfg80211) and are unable to cope with multiple registrations for the same frame type, which is valid due to the match filter. This seems to indicate the API is wrong, and we should maintain the full information in cfg80211 instead of the drivers. Change the API to no longer inform the driver about individual registrations and unregistrations, but rather every time about the entire state of the entire wiphy and single wdev, whenever it may have changed. This also simplifies the code in cfg80211 as it no longer has to track exactly what was unregistered and can free things immediately. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Acked-by: Arend van Spriel <arend.vanspriel@broadcom.com> Reviewed-by: Sergey Matyukevich <sergey.matyukevich.os@quantenna.com> Link: https://lore.kernel.org/r/20200417124300.f47f3828afc8.I7f81ef59c2c5a340d7075fb3c6d0e08e8aeffe07@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2020-04-24mac80211_hwsim: notify wmediumd of used MAC addressesJohannes Berg2-0/+59
Currently, wmediumd requires each used MAC address to be configured as a station in the virtual air, but that doesn't make sense as any station could have multiple MAC addresses, and even have randomized ones in scanning, etc. Add some code here to tell wmediumd of used MAC addresses, binding them to the hardware address. Combined with a wmediumd patch that makes it track the addresses this allows configuring just the radio address (42:00:00:00:nn:00 unless the radio was manually created) in wmediumd as a station, and all addresses that the station uses are added/removed dynamically. Tested with random scan, which without this and the corresponding wmediumd change doesn't get anything through as the sender doesn't exist as far as wmediumd is concerned (it's random). Link: https://lore.kernel.org/r/20200323162358.b397b1a1acef.Ice0536e34e5d96c51f97c374ea8af9551347c7e8@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
2020-04-23net: phy: bcm54140: fix less than zero comparison on an unsignedColin Ian King1-2/+4
Currently the unsigned variable tmp is being checked for an negative error return from the call to bcm_phy_read_rdb and this can never be true since tmp is unsigned. Fix this by making tmp a plain int. Addresses-Coverity: ("Unsigned compared against 0") Fixes: 4406d36dfdf1 ("net: phy: bcm54140: add hwmon support") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23qed: Make ll2_cbs staticZou Wei1-1/+1
Fix the following sparse warning: drivers/net/ethernet/qlogic/qed/qed_ll2.c:2334:20: warning: symbol 'll2_cbs' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Acked-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpsw: enable cpts irqGrygorii Strashko4-0/+55
The CPSW misc IRQ need be enabled for CPTS event_pend IRQs processing. This patch adds corresponding support to CPSW driver. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: add support for HW_TS_PUSH eventsGrygorii Strashko4-5/+57
Hence CPTS IRQ support is in place the W_TS_PUSH events can be added. PWM capable DmTimers can be used to generete input signals for CPTS on TI AM335x/AM437x/DRA7 SoCs to be timestamped: AM335x/AM437x: timer4 - timer7 DRA7/AM57xx: timer13 - timer16 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: add irq supportGrygorii Strashko2-1/+38
Add CPTS IRQ support, but do not enable it. By default, the CPTS driver will continue working using polling mode which is required for CPTS to continue working on platforms other than CPSW, like Keystone 2. The CPTS IRQ support is required to enable support for HW_TS_PUSH events. The CPSW CPTS IRQ and HW_TS_PUSH events support will be enabled in follow up patches. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: rework lockingGrygorii Strashko2-24/+32
Now spinlock is used to synchronize everything which is not required. Add mutex and use to sync access to PTP interface and PTP worker and use spinlock only to sync FIFO/events processing. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: move tx timestamp processing to ptp worker onlyGrygorii Strashko1-71/+94
Now the tx timestamp processing happens from different contexts - softirq and thread/PTP worker. Enabling IRQ will add one more hard_irq context. This makes over all defered TX timestamp processing and locking overcomplicated. Move tx timestamp processing to PTP worker always instead. napi_rx->cpts_tx_timestamp if ptp_packet then push to txq ptp_schedule_worker() do_aux_work->cpts_overflow_check cpts_process_events() Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: optimize packet to event matchingGrygorii Strashko1-33/+58
Now the CPTS driver performs packet (skb) parsing every time when it needs to match packet to CPTS event (including ptp_classify_raw() calls). This patch optimizes matching process by parsing packet only once upon arrival and stores PTP specific data in skb->cb using the same fromat as in CPTS HW event. As result, all future matching reduces to comparing two u32 values. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: switch to use new .gettimex64() interfaceGrygorii Strashko1-8/+14
The CPTS HW latches and saves CPTS counter value in CPTS fifo immediately after writing to CPSW_CPTS_PUSH.TS_PUSH (bit 0), so the total time that the driver needs to read the CPTS timestamp is the time required CPSW_CPTS_PUSH write to actually reach HW. Hence switch CPTS driver to implement new .gettimex64() callback for more precise measurement of the offset between a PHC and the system clock which is measured as time between write(CPSW_CPTS_PUSH) read(CPSW_CPTS_PUSH) Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: move tc mult update in cpts_fifo_read()Grygorii Strashko2-2/+7
Now CPTS driver .adjfreq() generates request to read CPTS current time (CPTS_EV_PUSH) with intention to process all pending event using previous frequency adjustment values before switching to the new ones. So CPTS_EV_PUSH works as a marker to switch to the new frequency adjustment values. Current code assumes that all job is done in .adjfreq(), but after enabling IRQ this will not be true any more. Hence save new frequency adjustment values (mult) and perform actual freq adjustment in cpts_fifo_read() immediately after CPTS_EV_PUSH is received. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: separate hw counter read from timecounterGrygorii Strashko2-26/+29
Now CPTS HW time reading code is implemented in timecounter->cyclecounter .read() callback and performs following operations: timecounter_read() ->cc.read() -> cpts_systim_read() - request current CPTS HW time CPTS_TS_PUSH.TS_PUSH = 1 - poll CPTS FIFO for CPTS_EV_PUSH event with current HW timestamp This approach need to be changed for the future switch to PTP PHC .gettimex64() callback, which require to separate requesting current CPTS HW time and processing CPTS FIFO. And for the follow up patch, which improves .adjfreq() implementation. This patch moves code accessing CPTS HW out of timecounter code as following: - convert HW timestamp of every CPTS event to PTP time (us) and store it as part struct cpts_event; - add CPTS context field to store current CPTS HW time (counter) value and update it on CPTS_EV_PUSH reception; - move code accessing CPTS HW out of timecounter code and use current CPTS HW time (counter) from CPTS context instead; - ensure timecounter->cycle_last is updated on CPTS_EV_PUSH reception. After this change CPTS timecounter will only perform timekeeper role without actually accessing CPTS HW. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net: ethernet: ti: cpts: use dev_yy() api for logsGrygorii Strashko1-6/+6
Use dev_yy() API instead of pr_yy() for log outputs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23net/mlx4_en: use napi_complete_done() in TX completionEric Dumazet3-13/+13
In order to benefit from the new napi_defer_hard_irqs feature, we need to use napi_complete_done() variant in this driver. RX path is already using it, this patch implements TX completion side. mlx4_en_process_tx_cq() now returns the amount of retired packets, instead of a boolean, so that mlx4_en_poll_tx_cq() can pass this value to napi_complete_done(). Signed-off-by: Eric Dumazet <edumazet@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23qede: Add support for handling the pcie errors.Sudarsana Reddy Kalluru2-1/+68
The error recovery is handled by management firmware (MFW) with the help of qed/qede drivers. Upon detecting the errors, driver informs MFW about this event which in turn starts a recovery process. MFW sends ERROR_RECOVERY notification to the driver which performs the required cleanup/recovery from the driver side. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-23qed: Enable device error reporting capability.Sudarsana Reddy Kalluru1-0/+9
The patch enables the device to send error messages to root port when an error is detected. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: use bulk enqueue in .ndo_xdp_xmitIoana Ciornei2-29/+30
Take advantage of the bulk enqueue feature in .ndo_xdp_xmit. We cannot use the XDP_XMIT_FLUSH since the architecture is not capable to store all the frames dequeued in a NAPI cycle so we instead are enqueueing all the frames received in a ndo_xdp_xmit call right away. After setting up all FDs for the xdp_frames received, enqueue multiple frames at a time until all are sent or the maximum number of retries is hit. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: split the .ndo_xdp_xmit callback into two stagesIoana Ciornei1-36/+40
Instead of having a function that both creates a frame descriptor from an xdp_frame and enqueues it, split this into two stages. Add the dpaa2_eth_xdp_create_fd that just transforms an xdp_frame into a FD while the actual enqueue callback is called directly from the ndo for each frame. This is particulary useful in conjunction with bulk enqueue. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: use the bulk ring mode enqueue interfaceIoana Ciornei2-14/+22
Update the dpaa2-eth driver to use the bulk enqueue function introduced with the change to QBMAN ring mode. At the moment, no functional changes are made but rather the driver just transitions to the new interface while still enqueuing just one frame at a time. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: return num_enqueued frames from enqueue callbackIoana Ciornei2-13/+26
The enqueue dpaa2-eth callback now returns the number of successfully enqueued frames. This is a preliminary patch necessary for adding support for bulk ring mode enqueue. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: tja11xx: add delayed registration of TJA1102 PHY1Oleksij Rempel1-7/+105
TJA1102 is a dual PHY package with PHY0 having proper PHYID and PHY1 having no ID. On one hand it is possible to for PHY detection by compatible, on other hand we should be able to reset complete chip before PHY1 configured it, and we need to define dependencies for proper power management. We can solve it by defining PHY1 as child of PHY0: tja1102_phy0: ethernet-phy@4 { reg = <0x4>; interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; reset-assert-us = <20>; reset-deassert-us = <2000>; tja1102_phy1: ethernet-phy@5 { reg = <0x5>; interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; }; }; The PHY1 should be a subnode of PHY0 and registered only after PHY0 was completely reset and initialized. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mdio: of: export part of of_mdiobus_register_phy()Oleksij Rempel1-31/+42
This function will be needed in tja11xx driver for secondary PHY support. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: tja11xx: add initial TJA1102 supportOleksij Rempel1-0/+91
TJA1102 is an dual T1 PHY chip. Both PHYs are separately addressable. Both PHYs are similar but have different amount of functionality. For example PHY 1 has no PHY ID and no health monitor. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: Use IS_ERR() to check and simplify codeTang Bin1-5/+2
Use IS_ERR() and PTR_ERR() instead of PTR_ZRR_OR_ZERO() to simplify code, avoid redundant paramenter definitions and judgements. Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com> Signed-off-by: Tang Bin <tangbin@cmss.chinamobile.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: micrel: add phy-mode support for the KSZ9031 PHYOleksij Rempel1-5/+123
Add support for following phy-modes: rgmii, rgmii-id, rgmii-txid, rgmii-rxid. This PHY has an internal RX delay of 1.2ns and no delay for TX. The pad skew registers allow to set the total TX delay to max 1.38ns and the total RX delay to max of 2.58ns (configurable 1.38ns + build in 1.2ns) and a minimal delay of 0ns. According to the RGMII v1.3 specification the delay provided by PCB traces should be between 1.5ns and 2.0ns. The RGMII v2.0 allows to provide this delay by MAC or PHY. So, we configure this PHY to the best values we can get by this HW: TX delay to 1.38ns (max supported value) and RX delay to 1.80ns (best calculated delay) The phy-modes can still be fine tuned/overwritten by *-skew-ps device tree properties described in: Documentation/devicetree/bindings/net/micrel-ksz90x1.txt Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: stmmac: Add support for VLAN promiscuous modeChuah, Kim Tatt3-0/+69
For dwmac4, enable VLAN promiscuity when MAC controller is requested to enter promiscuous mode. Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: Tan, Tee Min <tee.min.tan@intel.com> Signed-off-by: Wong Vee Khee <vee.khee.wong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22macvlan: silence RCU list debugging warningWei Yongjun1-1/+2
macvlan_hash_lookup() uses list_for_each_entry_rcu() for traversing should either under RCU in fast path or the protection of rtnl_mutex. In the case of holding RTNL, we should add the corresponding lockdep expression to silence the following false-positive warning: ============================= WARNING: suspicious RCU usage 5.7.0-rc1-next-20200416-00003-ga3b8d28bc #1 Not tainted ----------------------------- drivers/net/macvlan.c:126 RCU-list traversed in non-reader section!! Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: dsa: felix: allow flooding for all traffic classesXiaoliang Yang2-0/+8
Right now it can be seen that the VSC9959 (Felix) switch will not flood frames if they have a VLAN tag with a PCP of 1-7 (nonzero). It turns out that Felix is quite different from its cousin, Ocelot, in that frame flooding can be allowed/denied per traffic class. Where Ocelot has 1 instance of the ANA_FLOODING register, Felix has 8. The approach that this driver is going to take is "thanks, but no thanks". We have no use case of limiting the flooding domain based on traffic class, so we just want to allow packets to be flooded, no matter what traffic class they have. So we copy the line of code from ocelot.c which does the one-shot initialization of the flooding PGIDs, and we add it to felix.c as well - except replicated 8 times. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22r8169: use devm_mdiobus_registerHeiner Kallweit1-8/+2
Use new function devm_mdiobus_register() to simplify the driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: add device-managed devm_mdiobus_registerHeiner Kallweit1-1/+7
If there's no special ordering requirement for mdiobus_unregister(), then driver code can be simplified by using a device-managed version of mdiobus_register(). Prerequisite is that bus allocation has been done device-managed too. Else mdiobus_free() may be called whilst bus is still registered, resulting in a BUG_ON(). Therefore let devm_mdiobus_register() return -EPERM if bus was allocated non-managed. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: bcm54140: add hwmon supportMichael Walle2-0/+397
The PHY supports monitoring its die temperature as well as two analog voltages. Add support for it. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: add Broadcom BCM54140 supportMichael Walle3-0/+492
The Broadcom BCM54140 is a Quad SGMII/QSGMII Copper/Fiber Gigabit Ethernet transceiver. This also adds support for tunables to set and get downshift and energy detect auto power-down. The PHY has four ports and each port has its own PHY address. There are per-port registers as well as global registers. Unfortunately, the global registers can only be accessed by reading and writing from/to the PHY address of the first port. Further, there is no way to find out what port you actually are by just reading the per-port registers. We therefore, have to scan the bus on the PHY probe to determine the port and thus what address we need to access the global registers. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: phy: broadcom: add helper to write/read RDB registersMichael Walle2-0/+89
RDB (Register Data Base) registers are used on newer Broadcom PHYs. Add helper to read, write and modify these registers. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mscc: ocelot: lift protocol restriction for flow_match_eth_addrs keysVladimir Oltean1-5/+0
An attempt was made in commit fe3490e6107e ("net: mscc: ocelot: Hardware ofload for tc flower filter") to avoid clashes between MAC_ETYPE rules and IP rules. Because the protocol blacklist should have included ETH_P_ALL too, it created some confusion, but now the situation should be dealt with a bit better by the patch immediately previous to this one ("net: mscc: ocelot: refine the ocelot_ace_is_problematic_mac_etype function"). So now we can remove that check. MAC_ETYPE rules with a protocol of ETH_P_IP, ETH_P_IPV6, ETH_P_ARP and ETH_P_ALL _are_ supported, with some restrictions regarding per-port exclusivity which are enforced now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mscc: ocelot: refine the ocelot_ace_is_problematic_mac_etype functionVladimir Oltean1-4/+14
The commit mentioned below was a bit too harsh, and while it restricted the invalid key combinations which are known to not work, such as: tc filter add dev swp0 ingress proto ip \ flower src_ip 192.0.2.1 action drop tc filter add dev swp0 ingress proto all \ flower src_mac 00:11:22:33:44:55 action drop it also restricted some which still should work, such as: tc filter add dev swp0 ingress proto ip \ flower src_ip 192.0.2.1 action drop tc filter add dev swp0 ingress proto 0x22f0 \ flower src_mac 00:11:22:33:44:55 action drop What actually does not match "sanely" is a MAC_ETYPE rule on frames having an EtherType of ARP, IPv4, IPv6, in addition to SNAP and OAM frames (which the ocelot tc-flower implementation does not parse yet, so the function might need to be revisited again in the future). So just make the function recognize the problematic MAC_ETYPE rules by EtherType - thus the VCAP IS2 can be forced to match even on those packets. This patch makes it possible for IP rules to live on a port together with MAC_ETYPE rules that are non-all, non-arp, non-ip and non-ipv6. Fixes: d4d0cb741d7b ("net: mscc: ocelot: deal with problematic MAC_ETYPE VCAP IS2 rules") Reported-by: Allan W. Nielsen <allan.nielsen@microchip.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mscc: ocelot: support matching on EtherTypeVladimir Oltean1-3/+19
Currently, the filter's protocol is ignored except for a few special cases (IPv4 and IPv6). The EtherType can be matched inside VCAP IS2 by using a MAC_ETYPE key. So there are 2 cases in which EtherType matches are supported: - As part of a larger MAC_ETYPE rule, such as: tc filter add dev swp0 ingress protocol ip \ flower skip_sw src_mac 42:be:24:9b:76:20 action drop - Standalone (matching on protocol only): tc filter add dev swp0 ingress protocol arp \ flower skip_sw action drop As before, if the protocol is not specified, is it implicitly "all" and the EtherType mask in the MAC_ETYPE half key is set to zero. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: dsa: felix: enable PTP programmable pinYangbo Lu1-2/+4
Enable PTP programmable pin. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: enable PTP programmable pinYangbo Lu1-2/+4
Enable PTP programmable pin. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: support 4 PTP programmable pinsYangbo Lu1-0/+121
Support 4 PTP programmable pins with only PTP_PF_PEROUT function for now. The PTP_PF_EXTTS function will be supported in the future, and it should be implemented separately for Felix and Ocelot, because of different hardware interrupt implementation in them. Since the hardware is not able to support absolute start time, the periodic clock request only allows start time 0 0. But nsec could be accepted for PPS case for phase adjustment. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: add wave programming registers definitionsYangbo Lu2-0/+4
Add wave programming registers definitions for Ocelot platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: fix timestamp info if ptp clock does not workYangbo Lu1-0/+6
The timestamp info should be only software timestamp capabilities if ptp clock does not work. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: move ocelot ptp clock code out of ocelot.cYangbo Lu7-250/+255
The Ocelot PTP clock driver had been embedded into ocelot.c driver. It had supported basic gettime64/settime64/adjtime/adjfine functions by now which were used by both Ocelot switch and Felix switch. This patch is to move current ptp clock code out of ocelot.c driver maintaining as a single ocelot_ptp.c. For futher new features implementation, the common code could be put in ocelot_ptp.c and the switch specific code should be in specific switch driver. The interrupt implementation in SoC is different between Ocelot and Felix. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net/nfp: Update driver to use global kernel versionLeon Romanovsky2-5/+0
Change nfp driver to use globally defined kernel version. Reported-by: Borislav Petkov <bp@suse.de> Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net/hns: Remove custom driver version in favour of global oneLeon Romanovsky3-11/+0
Use globally defined kernel version instead of custom driver variant. Reported-by: Borislav Petkov <bp@suse.de> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21drivers: Remove inclusion of vermagic headerLeon Romanovsky6-6/+3
Get rid of linux/vermagic.h includes, so that MODULE_ARCH_VERMAGIC from the arch header arch/x86/include/asm/module.h won't be redefined. In file included from ./include/linux/module.h:30, from drivers/net/ethernet/3com/3c515.c:56: ./arch/x86/include/asm/module.h:73: warning: "MODULE_ARCH_VERMAGIC" redefined 73 | # define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY | In file included from drivers/net/ethernet/3com/3c515.c:25: ./include/linux/vermagic.h:28: note: this is the location of the previous definition 28 | #define MODULE_ARCH_VERMAGIC "" | Fixes: 6bba2e89a88c ("net/3com: Delete driver and module versions from 3com drivers") Co-developed-by: Borislav Petkov <bp@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Shannon Nelson <snelson@pensando.io> # ionic Acked-by: Sebastian Reichel <sre@kernel.org> # power Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: bcmgenet: Drop too many parentheses in bcmgenet_probe()Andy Shevchenko1-1/+1
No need to have parentheses around plain pointer variable or negation operator. Drop them for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 00:35:47 +0000