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2022-06-23nfp: add 'ethtool --identify' supportSixiang Chen3-0/+66
Add support for ethtool -p|--identify by enabling blinking of the panel LED if supported by the NIC firmware. Signed-off-by: Sixiang Chen <sixiang.chen@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Acked-by: Jakub Kicinski <kuba@kernel.org> Link: https://lore.kernel.org/r/20220622083938.291548-1-simon.horman@corigine.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-22Merge branch '40GbE' of ↵Jakub Kicinski3-6/+92
git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue Tony Nguyen says: ==================== 40GbE Intel Wired LAN Driver Updates 2022-06-21 This series contains updates to i40e driver only. Mateusz adds support for using the speed option in ethtool. Minghao Chi removes unneeded synchronize_irq() calls. Bernard Zhao removes unneeded NULL check. * '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue: intel/i40e: delete if NULL check before dev_kfree_skb i40e: Remove unnecessary synchronize_irq() before free_irq() i40e: Add support for ethtool -s <interface> speed <speed in Mb> ==================== Link: https://lore.kernel.org/r/20220621225930.632741-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22net: phy: Add support for AQR113C EPHYBhadram Varka1-0/+20
Add support multi-gigabit and single-port Ethernet PHY transceiver (AQR113C). Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Link: https://lore.kernel.org/r/20220621034027.56508-1-vbhadram@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22net: pcs: lynx: use mdiodev accessorsRussell King (Oracle)1-20/+10
Use the recently introduced mdiodev accessors for the lynx PCS. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/E1o3Zd8-002yHI-G2@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22isdn: mISDN: hfcsusb: drop unexpected word "the" in the commentsJiang Jian1-1/+1
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/isdn/hardware/mISDN/hfcsusb.c line: 1560 /* set USB_SIZE_I to match the the wMaxPacketSize for ISO transfers */ changed to /* set USB_SIZE_I to match the wMaxPacketSize for ISO transfers */ Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com> Link: https://lore.kernel.org/r/20220621114529.108079-1-jiangjian@cdjrlc.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22net: ipa: remove unexpected word "the"Jiang Jian1-2/+2
there is an unexpected word "the" in the comments that need to be removed Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com> Reviewed-by: Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20220621085001.61320-1-jiangjian@cdjrlc.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22cxgb4vf: remove unexpected word "the"Jiang Jian1-1/+1
there is an unexpected word "the" in the comments that need to be removed Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com> Link: https://lore.kernel.org/r/20220621084537.58402-1-jiangjian@cdjrlc.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22amt: remove unnecessary (void*) conversionsYu Zhe1-4/+4
Remove unnecessary void* type castings. Signed-off-by: Yu Zhe <yuzhe@nfschina.com> Acked-by: Taehee Yoo <ap420073@gmail.com> Link: https://lore.kernel.org/r/20220621021648.2544-1-yuzhe@nfschina.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-22mlxsw: spectrum_fid: Implement missing operations for rFID and dummy FIDAmit Cohen1-4/+54
rFID and dummy FID do not support FID->VNI mapping. Currently, these families do not implement the vni_{set, clear}() operations. Instead, there is a check if these functions are implemented. Similarly, 'SFMR.nve_tunnel_flood_ptr' is not relevant for rFID and dummy FID, therefore, these families do not implement nve_flood_index_{set, clear}(). Align the behavior to other unsupported operations, implement the functions and just return an error or warn. Then, checks like '!ops->vni_set' can be removed. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_fid: Use 'fid->fid_offset' when setting VNIAmit Cohen1-11/+14
The previous patch added 'fid_offset' field to FID structure. Now, this field can be used when VNI is set using SFMR register. Currently 'fid_offset' is set to zero, instead, use the new field which is now set to zero and in the future will be changed. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_fid: Save 'fid_offset' as part of FID structureAmit Cohen1-6/+23
SFMR register contains a 'fid_offset' field which is used when flooding tables of type FID offset are used. Currently, the driver sets this field to zero, as flooding tables of type FID are used. Using unified bridge model, the driver will use FID offset flooding tables. As preparation, add 'fid_offset' to 'struct mlxsw_sp_fid'. Then, use this field instead of passing zero to the function that configures SFMR. Set the new field as part of 'ops->setup()', for that, implement this function for dummy FID and rFID. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: pci: Query resources before and after issuing 'CONFIG_PROFILE' commandAmit Cohen1-0/+9
Currently, as part of mlxsw_pci_init(), resources are queried from firmware before issuing the 'CONFIG_PROFILE' command. There are resources whose size depend on the enablement of the unified bridge model that is performed via 'CONFIG_PROFILE' command. As a preparation for unified bridge model, add an additional query after issuing this command. Both queries are required as KVD sizes are read from firmware and then are configured as part of 'CONFIG_PROFILE' command. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: cmd: Increase 'config_profile.flood_mode' lengthAmit Cohen1-1/+1
Currently, the length of 'config_profile.flood_mode' is defined as 2 bits, while the correct length is 3 bits. As preparation for unified bridge model, which will use the whole field length, fix it and increase the field to the correct size. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: Add enumerator for 'config_profile.flood_mode'Amit Cohen2-8/+17
Currently magic constant is used for setting 'flood_mode' as part of config profile. As preparation for unified bridge model, which will require different 'flood_mode', add a dedicated enumerator for this field and use it as part of 'struct mlxsw_config_profile'. Add the relevant value for unified bridge model. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_switchdev: Handle error in mlxsw_sp_bridge_mdb_mc_enable_sync()Amit Cohen1-12/+31
The above mentioned function calls two functions which return values, but it ignores them. Check if the return value is an error, handle it in such case and return an error back to the caller. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_switchdev: Convert mlxsw_sp_mc_write_mdb_entry() to return intAmit Cohen1-7/+9
The function returns 'false' upon failure and 'true' upon success. Convert it to the usual scheme of returning integer error codes and align the callers. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_switchdev: Add error path in mlxsw_sp_port_mc_disabled_set()Amit Cohen1-2/+15
The above mentioned function just returns an error in case that mlxsw_sp_bridge_ports_flood_table_set() fails. That means that the previous configurations are not cleaned. Fix it by adding error path to clean the configurations in case of error. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_switchdev: Simplify mlxsw_sp_port_mc_disabled_set()Amit Cohen1-7/+66
The above mentioned function is called for each port in bridge when the multicast behavior is changed. Currently, it updates all the relevant MID entries only for the first call, but the update of flooding per port is done only for the port that it was called for it. To simplify this behavior, it is possible to handle flooding for all the ports in the first call, then, the other calls will do nothing. For that, new functions are required to set flooding for all ports, no 'struct mlxsw_sp_port' is required. This issue was found while extending this function for unified bridge model, the above mentioned change will ease the extending later. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_switchdev: Do not set 'multicast_enabled' twiceAmit Cohen1-2/+0
The function mlxsw_sp_port_mc_disabled_set() sets 'bridge_device->multicast_enabled' twice. Remove the unnecessary setting. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: spectrum_switchdev: Pass 'struct mlxsw_sp' to ↵Amit Cohen1-7/+4
mlxsw_sp_bridge_mdb_mc_enable_sync() Currently the above mentioned function gets 'struct mlxsw_sp_port', while the only use of this structure is to get 'mlxsw_sp_port->mlxsw_sp'. Instead, pass 'struct mlxsw_sp'. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-22mlxsw: Remove lag_vid_valid indicationAmit Cohen3-11/+1
Currently 'struct mlxsw_sp_fid_family' has a field which indicates if 'lag_vid' is valid for use in SFD register. This is a leftover from using .1Q FIDs instead of emulating them using .1D FIDs. Currently when .1Q FIDs are emulated using .1D FIDs, this field is true for both families, so there is no reason to maintain it. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-21net: phy: dp83td510: add SQI supportOleksij Rempel1-0/+49
Convert MSE (mean-square error) values to SNR and split it SQI (Signal Quality Indicator) ranges. The used ranges are taken from "OPEN ALLIANCE - Advanced diagnostic features for 100BASE-T1 automotive Ethernet PHYs" specification. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220620115601.2035452-1-o.rempel@pengutronix.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-21net: phy: smsc: Deduplicate interrupt acknowledgement upon phy_init_hw()Lukas Wunner1-12/+1
Since commit 4c0d2e96ba05 ("net: phy: consider that suspend2ram may cut off PHY power"), phy_init_hw() invokes both, the ->config_init() and ->config_intr() callbacks. In the SMSC PHY driver, the latter acknowledges stale interrupts, hence there's no longer a need to acknowledge them in the former as well. There are no other callers of ->config_init() besides phy_init_hw(). Drop the redundant code. Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/0254edf48bddc96c6248c4414043a3699e94614a.1655716767.git.lukas@wunner.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-21intel/i40e: delete if NULL check before dev_kfree_skbBernard Zhao1-4/+2
dev_kfree_skb check if the input parameter NULL and do the right thing, there is no need to check again. This change is to cleanup the code a bit. Signed-off-by: Bernard Zhao <zhaojunkui2008@126.com> Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2022-06-21i40e: Remove unnecessary synchronize_irq() before free_irq()Minghao Chi1-2/+0
Calling synchronize_irq() right before free_irq() is quite useless. On one hand the IRQ can easily fire again before free_irq() is entered, on the other hand free_irq() itself calls synchronize_irq() internally (in a race condition free way), before any state associated with the IRQ is freed. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2022-06-21i40e: Add support for ethtool -s <interface> speed <speed in Mb>Mateusz Palczewski1-0/+90
Add ability to change speed through ethtool -s <interface> speed <speed in Mb> Driver advertises all link modes that support requested speed. Autoneg must be set off e.g.: ethtool -s <interface> autoneg off speed <speed in Mb>. Add helper function that translate speed in Mb to enum i40e_aq_link_speed and compare it to supported speeds from given ethtool_link_ksettings. Add in i40e_set_link_ksettings hold for requested speed and set copy_ks.base.speed to safe_ks.base.speed to be sure that user is not changing unsupported setting. In i40e_speed_to_link_speed compare requested speed with supported speeds. Set speed to requested speed. Signed-off-by: Norbert Zulinski <norbertx.zulinski@intel.com> Signed-off-by: Mateusz Palczewski <mateusz.palczewski@intel.com> Tested-by: Dave Switzer <david.switzer@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2022-06-21net: dsa: microchip: move get_phy_flags & mtu to ksz_commonArun Ramadoss4-18/+52
This patch assigns the get_phy_flags & mtu hook of ksz8795 and ksz9477 in dsa_switch_ops to ksz_common. For get_phy_flags hooks,checks whether the chip is ksz8863/kss8793 then it returns error for port1. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: update fdb add/del/dump in ksz_commonArun Ramadoss4-51/+85
This patch makes the dsa_switch_hook for fdbs to use ksz_common.c file. And from ksz_common, individual switches fdb functions are called using the dev->dev_ops. And removed the r_dyn_mac_table, r_sta_mac_table and w_sta_mac_table from ksz_dev_ops as it is used only in ksz8795.c Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: update the ksz_port_mdb_add/delArun Ramadoss4-68/+98
ksz_mdb_add/del in ksz_common.c is specific for the ksz8795.c file. The ksz9477 has its separate ksz9477_port_mdb_add/del functions. This patch moves the ksz8795 specific mdb functionality from ksz_common to ksz8795. And this dsa_switch_ops hooks for ksz8795/ksz9477 are invoked through the ksz_port_mdb_add/del. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: update the ksz_phylink_get_capsArun Ramadoss4-10/+11
This patch assigns the phylink_get_caps in ksz8795 and ksz9477 to ksz_phylink_get_caps. And update their mac_capabilities in the respective ksz_dev_ops. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: get P_STP_CTRL in ksz_port_stp_state by ksz_dev_opsArun Ramadoss4-22/+24
At present, P_STP_CTRL register value is passed as parameter to ksz_port_stp_state from the individual dsa_switch_ops hooks. This patch update the function to retrieve the register value through the ksz_chip_data member. And add the static to ksz_update_port_member since it is not called outside the ksz_common. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: move the port mirror to ksz_commonArun Ramadoss4-13/+45
This patch updates the common port mirror add/del dsa_switch_ops in ksz_common.c. The individual switches implementation is executed based on the ksz_dev_ops function pointers. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: move vlan functionality to ksz_commonArun Ramadoss4-20/+69
This patch moves the vlan dsa_switch_ops such as vlan_add, vlan_del and vlan_filtering from the individual files ksz8795.c, ksz9477.c to ksz_common.c file. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: ksz9477: use ksz_read_phy16 & ksz_write_phy16Arun Ramadoss1-13/+10
ksz8795 and ksz9477 implementation on phy read/write hooks are different. This patch modifies the ksz9477 implementation same as ksz8795 by updating the ksz9477_dev_ops structure. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: move tag_protocol to ksz_commonArun Ramadoss4-25/+28
This patch move the dsa hook get_tag_protocol to ksz_common file. And the tag_protocol is returned based on the dev->chip_id. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: move switch chip_id detection to ksz_commonArun Ramadoss6-90/+93
KSZ87xx and KSZ88xx have chip_id representation at reg location 0. And KSZ9477 compatible switch and LAN937x switch have same chip_id detection at location 0x01 and 0x02. To have the common switch detect functionality for ksz switches, ksz_switch_detect function is introduced. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21net: dsa: microchip: ksz9477: cleanup the ksz9477_switch_detectArun Ramadoss1-26/+22
The ksz9477_switch_detect performs the detecting the chip id from the location 0x00 and also check gigabit compatibility check & number of ports based on the register global_options0. To prepare the common ksz switch detect function, routine other than chip id read is moved to ksz9477_switch_init. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-21nfp: compose firmware file name with new hwinfo "nffw.partno"Yu Xiao1-1/+3
During initialization of the NFP driver, a file name for loading application firmware is composed using the NIC's AMDA information and port type (count and speed). E.g.: "nic_AMDA0145-1012_2x10.nffw". In practice there may be many variants for each NIC type, and many of the variants relate to assembly components which do not concern the driver and application firmware implementation. Yet the current scheme leads to a different application firmware file name for each variant, because they have different AMDA information. To reduce proliferation of content-duplicated application firmware images or symlinks, the NIC's management firmware will only expose differences between variants that need different application firmware via a newly introduced hwinfo, "nffw.partno". Use of the existing hwinfo, "assembly.partno", is maintained in order to support for NICs with management firmware that does not expose "nffw.partno". Signed-off-by: Yu Xiao <yu.xiao@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Reviewed-by: Jakub Kicinski <kuba@kernel.org> Link: https://lore.kernel.org/r/20220620103912.46164-1-simon.horman@corigine.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-06-20mlxsw: reg: Add support for VLAN RIF as part of RITR registerAmit Cohen1-3/+26
Router interfaces (RIFs) constructed on top of VLAN-aware bridges are of "VLAN" type, whereas RIFs constructed on top of VLAN-unaware bridges of "FID" type. In other words, the RIF type is derived from the underlying FID type. VLAN RIFs are used on top of 802.1Q FIDs, whereas FID RIFs are used on top of 802.1D FIDs. Currently 802.1Q FIDs are emulated using 802.1D FIDs, and therefore VLAN RIFs are emulated using FID RIFs. As part of converting the driver to use unified bridge, 802.1Q FIDs and VLAN RIFs will be used. Add the relevant fields to RITR register, add pack() function for VLAN RIF and rename one field to fit the internal name. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: Add support for egress FID classification after decapsulationAmit Cohen2-9/+44
As preparation for unified bridge model, add support for VNI->FID mapping via SVFA register. When performing VXLAN encapsulation, the VXLAN header needs to contain a VNI. This VNI is derived from the FID classification performed on ingress, through which the ingress RIF is also determined. Similarly, when performing VXLAN decapsulation, the FID of the packet needs to be determined. This FID is derived from VNI classification performed during decapsulation. In the old model, both entries (i.e., FID->VNI and VNI->FID) were configured via SFMR.vni. In the new model, where ingress is separated from egress, ingress configuration (VNI->FID) is performed via SVFA, while SFMR only configures egress (FID->VNI). Add 'vni' field to SVFA, add new mapping table - VNI to FID, add new pack() function for VNI mapping and edit the comment in SFMR. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add egress FID field to RITR registerAmit Cohen1-2/+14
RITR configures the router interface table. As preparation for unified bridge model, add egress FID field to RITR. After routing, a packet has to perform a layer-2 lookup using the destination MAC it got from the routing and a FID. In the new model, the egress FID is configured by RITR for both sub-port and FID RIFs. Add 'efid' field to sub-port router interface and update FID router interface related comment. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add Router Egress Interface to VID RegisterAmit Cohen1-0/+59
The REIV maps {egress router interface (eRIF), egress_port} -> {vlan ID}. As preparation for unified bridge model, add REIV register for future use. In the past, firmware would take care of the above mentioned mapping, but in the new model this should be done by software using REIV register. REIV register supports a simultaneous update of 256 ports using 'port_page' field. When 'port_page'=0 the records represent ports 0-255, when 'port_page'=1 the records represent ports 256-511 and so on. The register is reserved while using the legacy model. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Replace MID related fields in SFGC registerAmit Cohen2-10/+9
SFGC register maps {packet type, bridge type} -> {MID base, table type}. As preparation for unified bridge model, remove 'mid' field and add 'mid_base' field. The MID index (index to PGT table which maps MID to local port list and SMPE index) is a result of 'mid_base' + 'fid_offset'. Using the legacy bridge model, firmware configures 'mid_base'. However, using the new model, software is responsible to configure it via SFGC register. The 'mid_base' is configured per {packet type, bridge type}, for example, for {Unicast, .1Q}, {Broadcast, .1D}. Add the field 'mid_base' to SFGC register and increase the length of the register accordingly. Remove the field 'mid' as currently it is ignored by the device, its use is an old leftover. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add flood related field to SFMR registerAmit Cohen1-0/+10
SFMR register creates and configures FIDs. As preparation for unified bridge model, add a required field for future use. The PGT (Port Group) table maps multicast ID (MID) to {local port list, SMPE index} on Spectrum-1 and to {local port list} on the other ASICs. In the legacy model, software did not interact with this table directly. Instead, it was accessed by firmware in response to registers such as SFTR and SMID. In the new model, the SFTR register is deprecated and software has full control over the PGT table using the SMID register. The configuration of MDB entries (using SFD) is unchanged, but flooding configuration is completely different. SFGC register maps {packet type, bridge type} -> {MID base, table type}, then with FID and FID-offset which are configured via SFMR, the MID index is obtained. Add the field 'flood_bridge_type' to SFMR, software can separate between 802.1q FIDs and vFIDs using two types which are supported. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add VID related fields to SFD registerAmit Cohen1-1/+36
SFD register configures FDB table. As preparation for unified bridge model, add some required fields for future use. In the new model, firmware no longer configures the egress VID, this responsibility is moved to software. For layer 2 this means that software needs to determine the egress VID for both unicast and multicast. For unicast FDB records and unicast LAG FDB records, the VID needs to be set via new fields in SFD - 'set_vid' and 'vid'. Add the two mentioned fields for future use. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add SMPE related fields to SFMR registerAmit Cohen1-1/+20
SFMR register creates and configures FIDs. As preparation unified bridge model, add some required fields for future use. The device includes two main tables to support layer 2 multicast (i.e., MDB and flooding). These are the PGT (Port Group Table) and the MPE (Multicast Port Egress) table. - PGT is {MID -> (bitmap of local_port, SPME index)} - MPE is {(Local port, SMPE index) -> eVID} In Spectrum-2 and later ASICs, the SMPE index is an attribute of the FID and programmed via new fields in SFMR register - 'smpe_valid' and 'smpe'. Add the two mentioned fields for future use and increase the length of the register accordingly. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: Add SMPE related fields to SMID2 registerAmit Cohen2-4/+24
SMID register maps multicast ID (MID) into a list of local ports. As preparation for unified bridge model, add some required fields for future use. The device includes two main tables to support layer 2 multicast (i.e., MDB and flooding). These are the PGT (Port Group Table) and the MPE (Multicast Port Egress) table. - PGT is {MID -> (bitmap of local_port, SPME index)} - MPE is {(Local port, SMPE index) -> eVID} In Spectrum-1, both indexes into the MPE table (local port and SMPE) are derived from the PGT table. Therefore, the SMPE index needs to be programmed as part of the PGT entry via new fields in SMID - 'smpe_valid' and 'smpe'. Add the two mentioned fields for future use and align the callers of mlxsw_reg_smid2_pack() to pass zeros for SMPE fields. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add Switch Multicast Port to Egress VID RegisterAmit Cohen1-0/+40
The SMPE register maps {egress_port, SMPE index} -> VID. The device includes two main tables to support layer 2 multicast (i.e., MDB and flooding). These are the PGT (Port Group Table) and the MPE (Multicast Port Egress) table. - PGT is {MID -> (bitmap of local_port, SPME index)} - MPE is {(Local port, SMPE index) -> eVID} In Spectrum-1, the index into the MPE table - called switch multicast to port egress VID (SMPE) - is derived from the PGT entry, whereas in Spectrum-2 and later ASICs it is derived from the FID. In the legacy model, software did not interact with this table as it was completely hidden in firmware. In the new model, software needs to populate the table itself in order to map from {Local port, SMPE index} to an egress VID. This is done using the SMPE register. Add the register for future use. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add ingress RIF related fields to SVFA registerAmit Cohen1-1/+21
SVFA register controls the VID to FID mapping and {Port, VID} to FID mapping for virtualized ports. As preparation for unified bridge model, add some required fields for future use. On ingress, after ingress ACL, a packet needs to be classified to a FID. The key for this lookup can be one of: 1. VID. When port is not in virtual mode. 2. {RQ, VID}. When port is in virtual mode. 3. FID. When FID was set by ingress ACL. Since RITR no longer performs ingress configuration, the ingress RIF for the first two entry types needs to be set via new fields in SVFA - 'irif_v' and 'irif'. Add the two mentioned fields for future use and increase the length of the register accordingly. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-20mlxsw: reg: Add ingress RIF related fields to SFMR registerAmit Cohen1-0/+20
SFMR register creates and configures FIDs. As preparation for unified bridge model, add some required fields for future use. On ingress, after ingress ACL, a packet needs to be classified to a FID. The key for this lookup can be one of: 1. VID. When port is not in virtual mode. 2. {RQ, VID}. When port is in virtual mode. 3. FID. When FID was set by ingress ACL. For example, via VR_AND_FID_ACTION. Since RITR no longer performs ingress configuration, the ingress RIF for the last entry type needs to be set via new fields in SFMR - 'irif_v' and 'irif'. Add the two mentioned fields for future use. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-08 19:20:20 +0000