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2017-06-13networking: use skb_put_zero()Johannes Berg5-10/+6
Use the recently introduced helper to replace the pattern of skb_put() && memset(), this transformation was done with the following spatch: @@ identifier p; expression len; expression skb; @@ -p = skb_put(skb, len); -memset(p, 0, len); +p = skb_put_zero(skb, len); Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: phy: Make phy_ethtool_ksettings_get return voidyuval.shaia@oracle.com19-46/+61
Make return value void since function never return meaningfull value Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13mdio_bus: use devm_gpiod_get_optional()Sergei Shtylyov1-9/+5
The MDIO reset GPIO is really a classical optional GPIO property case, so devm_gpiod_get_optional() should have been used, not devm_gpiod_get(). Doing this saves several LoCs... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13mdio_bus: handle only single PHY reset GPIOSergei Shtylyov2-35/+19
Commit 4c5e7a2c0501 ("dt-bindings: mdio: Clarify binding document") declared that a MDIO reset GPIO property should have only a single GPIO reference/specifier, however the supporting code was left intact, still burdening the kernel with now apparently useless loops -- get rid of them. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13ibmvnic: Remove netdev notify for failover resetsNathan Fontenot1-1/+3
When handling a driver reset due to a failover of the backing server on the vios, doing the netdev_notify_peers() can cause network traffic to stall or halt. Remove the netdev notify call for failover resets. Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13ibmvnic: Client-initiated failoverThomas Falcon1-0/+46
The IBM vNIC protocol provides support for the user to initiate a failover from the client LPAR in case the current backing infrastructure is deemed inadequate or in an error state. Support for two H_VIOCTL sub-commands for vNIC devices are required to implement this function. These commands are H_GET_SESSION_TOKEN and H_SESSION_ERR_DETECTED. "[H_GET_SESSION_TOKEN] is used to obtain a session token from a VNIC client adapter. This token is opaque to the caller and is intended to be used in tandem with the SESSION_ERROR_DETECTED vioctl subfunction." "[H_SESSION_ERR_DETECTED] is used to report that the currently active backing device for a VNIC client adapter is behaving poorly, and that the hypervisor should attempt to fail over to a different backing device, if one is available." To provide tools access to this functionality the vNIC driver creates a sysfs file that, when written to, will send a request to pHyp to failover to a different backing device. Signed-off-by: Thomas Falcon <tlfalcon@linux.vnet.ibm.com> Reviewed-by: Nathan Fontenot <nfont@linux.vnet.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: mvpp2: enable basic 10G supportAntoine Ténart1-8/+41
On GOP port 0 two MAC modes are available: GMAC and XLG. The XLG MAC is used for 10G connectivity. This patch adds a basic 10G support by allowing to use the XLG MAC on port 0 and by reworking the port_enable/disable functions so that the XLG MAC is configured when using 10G. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix remaining port macrosVivien Didelot3-13/+32
For implicit namespacing and clarity, prefix the remaining common Port Registers macros with MV88E6XXX_PORT. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port IEEE Priority mapping macrosVivien Didelot2-29/+38
For implicit namespacing and clarity, prefix the common Port IEEE Priority Remapping registers macros with MV88E6095_PORT_IEEE_PRIO. The 88E6390 family turned the 0x18 register into a single indirect table, document that at the same time. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Also fix the following checkpatch checks with a temporary variable: CHECK: Alignment should match open parenthesis #65: FILE: drivers/net/dsa/mv88e6xxx/port.c:932: + err = mv88e6xxx_port_ieeepmt_write(chip, port, + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP, Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Association Vector macrosVivien Didelot2-7/+10
For implicit namespacing and clarity, prefix the common Port Association Vector Register macros with MV88E6XXX_PORT_ASSOC_VECTOR. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Egress Rate Control macrosVivien Didelot3-5/+12
For implicit namespacing and clarity, prefix the common Port Egress Rate Control and Port Egress Rate Control 2 registers macros with MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control 2 macrosVivien Didelot3-48/+50
For implicit namespacing and clarity, prefix the common Port Control 2 Register macros with MV88E6XXX_PORT_CTL2 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6095_PORT_CTL2_CPU_PORT_MASK.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Default VLAN macrosVivien Didelot3-9/+14
For implicit namespacing and clarity, prefix the common Port Default VLAN Register macros with MV88E6XXX_PORT_DEFAULT_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Based VLAN macrosVivien Didelot2-7/+9
For implicit namespacing and clarity, prefix the common Port Based VLAN Register macros with MV88E6XXX_PORT_BASE_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control 1 macrosVivien Didelot2-10/+15
For implicit namespacing and clarity, prefix the common Port Control 1 Register macros with MV88E6XXX_PORT_CTL1. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control macrosVivien Didelot3-77/+79
For implicit namespacing and clarity, prefix the common Port Control Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6185_PORT_CTL0_USE_TAG.) The reason for CTL0 is to make it clear between the badly named "Port Control", "Port Control 1" and "Port Control 2" registers. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Switch ID macrosVivien Didelot2-57/+61
For implicit namespacing and clarity, prefix the common Switch ID Register macros with MV88E6XXX_PORT_SWITCH_ID. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers, this means shifting their values by 4. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Jamming macrosVivien Didelot2-9/+22
For implicit namespacing and clarity, prefix the common Port Jamming Control Register macros with MV88E6XXX_PORT_JAM_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6097_PORT_JAM_CTL.) The 88E6390 family renamed the register to Flow Control and turned it into an indirect table. Document that as well. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port MAC Control macrosVivien Didelot2-56/+64
For implicit namespacing and clarity, prefix the common MAC Control Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6065_PORT_MAC_CTL_SPEED_200.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Status macrosVivien Didelot4-54/+56
For implicit namespacing and clarity, prefix the common Port Status Register macros with MV88E6XXX_PORT_STS and the ones which differ between implementations with a chosen reference model (e.g. MV88E6352_PORT_STS_EEE.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-12net: phy: marvell: Show complete link partner advertisingThomas Bogendoerfer1-7/+0
Give back all modes advertised by the link partner. This change brings the marvell phy driver in line with all other phy drivers. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-12vxlan: dont migrate permanent fdb entries during learnRoopa Prabhu1-1/+1
This patch fixes vxlan_snoop to not move permanent fdb entries on learn events. This is consistent with the bridge fdb handling of permanent entries. Fixes: 26a41ae60438 ("vxlan: only migrate dynamic FDB entries") Signed-off-by: Roopa Prabhu <roopa@cumulusnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-12Merge tag 'wireless-drivers-next-for-davem-2017-06-12' of ↵David S. Miller152-3509/+16684
git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Valo says: ==================== wireless-drivers-next patches for 4.13 The first pull request for 4.13. We have a new driver qtnfmac, but also rsi driver got a support for new firmware and supporting ath10k SDIO devices was started. Major changes: ath10k * add initial SDIO support (still work in progress) rsi * new loading for the new firmware version rtlwifi * final patches for the new btcoex support rt2x00 * add device ID for Epson WN7512BEP qtnfmac * new driver for Quantenna QSR10G chipsets ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-12sh_eth: add support for changing MTUNiklas Söderlund1-0/+20
The hardware supports the MTU to be changed and the driver it self is somewhat prepared to support this. This patch hooks up the callbacks to be able to change the MTU from user-space. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-11Merge tag 'mlx5-updates-2017-06-11' of ↵David S. Miller6-67/+284
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-updates-2017-06-11 This series provides updates to mlx5 header rewrite feature, from Or Gerlitz. and three more small updates From maor and eran. ------- Or says: Packets belonging to flows which are different by matching may still need to go through the same header re-writes (e.g set the current routing hop MACs and issue TTL decrement). To minimize the number of modify header IDs, we add a cache for header re-write IDs which is keyed by the binary chain of modify header actions. The caching is supported for both eswitch and NIC use-cases, where the actual conversion of the code to use caching comes in separate patches, one per use-case. Using a per field mask field, the TC pedit action supports modifying partial fields. The last patch enables offloading that. ------- From Maor, update flow table commands layout to the latest HW spec. From Eran, ethtool connector type reporting updates. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-10net: ethernet: ti: cpdma: do not enable host error misc irqGrygorii Strashko1-4/+1
CPSW driver does not handle this interrupt, so there are no reasons to enable it in hardware. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-10net: ethernet: ti: cpsw: enable HWTSTAMP_FILTER_PTP_V1_L4_EVENT filterGrygorii Strashko1-4/+8
CPSW driver supports PTP v1 messages, but for unknown reasons this filter is not advertised. As result, ./tools/testing/selftests/networking/timestamping/timestamping utility can't be used for testing of CPSW RX timestamping with option SOF_TIMESTAMPING_RX_HARDWARE, because it uses HWTSTAMP_FILTER_PTP_V1_L4_SYNC filter. Hence, fix it by advertising HWTSTAMP_FILTER_PTP_V1_L4_XXX filters in CPSW driver. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-10net: fec: Add a fec_enet_clear_ethtool_stats() stub for CONFIG_M5272Fabio Estevam1-0/+4
Commit 2b30842b23b9 ("net: fec: Clear and enable MIB counters on imx51") introduced fec_enet_clear_ethtool_stats(), but missed to add a stub for the CONFIG_M5272=y case, causing build failure for the m5272c3_defconfig. Add the missing empty stub to fix the build failure. Fixes: Commit 2b30842b23b9 ("net: fec: Clear and enable MIB counters on imx51") Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-10bonding: warn user when 802.3ad speed is unknownNicolas Dichtel1-0/+5
Goal is to advertise the user when ethtool speeds and 802.3ad speeds are desynchronized. When this case happens, the kernel needs to be patched. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Dichtel <nicolas.dichtel@6wind.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09cxgb4: fix memory leak in init_one()Ganesh Goudar1-1/+5
Free up mbox_log allocated for PF0 to PF3. Fixes: 7829451c695e ("cxgb4: Add control net_device for configuring PCIe VF") Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: add qed_int_sb_init() stub functionArnd Bergmann1-0/+5
When CONFIG_QED_SRIOV is disabled, we get a build error: drivers/net/ethernet/qlogic/qed/qed_int.c: In function 'qed_int_sb_init': drivers/net/ethernet/qlogic/qed/qed_int.c:1499:4: error: implicit declaration of function 'qed_vf_set_sb_info'; did you mean 'qed_mcp_get_resc_info'? [-Werror=implicit-function-declaration] All the other declarations have a 'static inline' stub as an alternative here, so this adds one more for qed_int_sb_init. Fixes: 50a207147fce ("qed: Hold a single array for SBs") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: collect GSI port statisticsMintz, Yuval1-0/+23
The LL2 statistics already have place holders for these, but haven't populated them so far. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: Call rx_release_cb() when flushing LL2Mintz, Yuval1-6/+7
Driver to inform the connection owner that the its buffers are being released as part of a flush. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: No need for LL2 frags indicationMintz, Yuval1-23/+8
This is a legacy leftover; There's no current flow where 'frags_mapped' would be set. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed*: LL2 callback operationsMichal Kalderon8-505/+320
LL2 today is interrupt driven - when tx/rx completion arrives [or any other indication], qed needs to operate on the connection and pass the information to the protocol-driver [or internal qed consumer]. Since we have several flavors of ll2 employeed by the driver, each handler needs to do an if-else to determine the right functionality to use based on the connection type. In order to make things more scalable [given that we're going to add additional types of ll2 flavors] move the infrastrucutre into using a callback-based approach - the callbacks would be provided as part of the connection's initialization parameters. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: LL2 code relocationsMintz, Yuval1-30/+28
Instead of having the OOO logic packetd, divide it with rest of code according to establish/release flows. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: Cleaner seperation of LL2 inputsMintz, Yuval3-229/+223
A LL2 connection [qed_ll2_info] has a sub-structure of type qed_ll2_conn that contain various inputs for ll2 acquisition, but the connection also utilizes a couple of other inputs. Restructure the input structure to include all the inputs and refactor the code necessary to populate those. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: Revise ll2 Rx completionMintz, Yuval1-34/+50
This introduces qed_ll2_comp_rx_data as a public struct and moves handling of Rx packets in LL2 into using it. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09qed: LL2 to use packed information for txMintz, Yuval3-111/+75
First step in revising the LL2 interface, this declares qed_ll2_tx_pkt_info as part of the ll2 interface, and uses it for transmission instead of receiving lots of parameters. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: replace napi_complete with napi_complete_donehayeswang1-1/+3
Change from using napi_complete to napi_complete_done to allow for the use of gro_flush_timeout in tuning network processing. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: avoid rx queue more than 1000 packetshayeswang1-0/+4
Stop queuing rx packets if it is more than 1000. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: check if disabling ALDPS is finishedhayeswang1-1/+7
Use PLA 0xe000 bit 8 to check if disabling ALDPS is finished. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: move the initialization to reset_resume functionhayeswang1-4/+5
Move tp->rtl_ops.init() from rtl8152_resume() to rtl8152_reset_resume(). The initialization is only necessary for reset_resume(). Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: move the default coalesce setting for RTL8153hayeswang1-13/+13
Only RTL8153 could set coalesce, so move the default setting for rtl8152_probe() to r8153_init(). Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: adjust U2P3 for RTL8153hayeswang1-4/+37
Use another way to keep disabling the U2P3 for both RTL_VER_03 and RTL_VER_04. Move enabling U2P3 from r8153_init() to r8153_hw_phy_cfg(). The engineer ask the setting should be done after PHY settings. Disable U2P3 first in rtl8153_up(). Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: adjust rtl8153_runtime_enable functionhayeswang1-2/+2
Adjust the order of rtl8153_runtime_enable() according to the suggestion from the engineer. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: move the setting of rx aggregationhayeswang1-5/+4
Move the setting from r8153_first_init() to r8153_init(). It only needs to be set once. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: adjust the settings about MAC clock speed down for RTL8153hayeswang1-5/+29
The MAC clock speed down could be enabled if the U1/U2 is disabled. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: adjust lpm settings for RTL8153hayeswang1-4/+1
Enable lpm after r8153_init() and remove other enable/disable lpm. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09r8152: add r8153_phy_status functionhayeswang1-12/+25
Use r8153_phy_status() to check phy status of RTL8153. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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