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2013-04-17Merge tag 'davinci-for-v3.10/dt-2-v2' of ↵Olof Johansson2-7/+85
git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt2 From Sekhar Nori: v3.10 DT updates for DaVinci This set of patches adds support for PWMs and SPI controller present on DA850 and for SPI flash present on DA850 EVM. * tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: da850-evm: add SPI flash support ARM: davinci: da850: override SPI DT node device name ARM: davinci: da850: add SPI1 DT node spi/davinci: add DT binding documentation spi/davinci: no wildcards in DT compatible property ARM: davinci: da850: add EHRPWM & ECAP DT node ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: davinci: da850: add tps6507x regulator DT data ARM: regulator: add tps6507x device tree data ARM: davinci: remove test for undefined Kconfig macro ARM: davinci: mmc: derive version information from device name ARM: davinci: da850: add ECAP & EHRPWM clock nodes ARM: davinci: clk framework support for enable/disable functionality Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-17Merge tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux into ↵Olof Johansson3-0/+878
next/dt2 From Jason Cooper: mvebu dt for v3.10 round 4 - mvebu LPAE 64bit dts file changes * tag 'dt-3.10-4' of git://git.infradead.org/users/jcooper/linux: (52 commits) ARM: dts: mvebu: Convert mvebu device tree files to 64 bits ARM: dts: mvebu: introduce internal-regs node ARM: dts: mvebu: Convert all the mvebu files to use the range property ARM: dts: mvebu: move all peripherals inside soc ARM: dts: mvebu: fix cpus section indentation arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-17spi/davinci: no wildcards in DT compatible propertyManjunathappa, Prakash1-2/+2
Follow DT naming convention for compatible property of the blob. Use first chip name that introduced the specific version of the device. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2013-04-12Merge tag 'dt-exynos-for-v3.10' of ↵Olof Johansson13-2/+3476
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt2 update device tree for exynos4 and exynos5 * tag 'dt-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (125 commits) ARM: dts: add PDMA0 changes for exynos5440 ARM: dts: Add cpufreq controller node for Exynos5440 SoC ARM: dts: Fix gmac clock ids due to changes in Exynos5440 ARM: dts: add device tree file for SD5v1 board ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440 ARM: dts: add PMU support in exynos5440 ARM: dts: Add node for GMAC for exynos5440 ARM: dts: list the interrupts generated by pin-controller on Exynos5440 ARM: dts: Add FIMD DT binding Documentation ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts ARM: dts: Add FIMD node to exynos4 ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series ARM: dts: Add display timing node to exynos5250-smdk5250.dts ARM: dts: Add FIMD node to exynos5 ARM: dts: Add virtual GIC DT bindings for exynos5440 ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings ARM: dts: add usb 2.0 clock references to exynos5250 device tree ARM: dts: Add architected timer nodes for exynos5250 ARM: dts: Declare the gic as a15 compatible for exynos5250 ARM: dts: Add HDMI HPD and regulator node for Arndale board ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-11bus: mvebu: fix mistake in PCIe window target attribute for KirkwoodThomas Petazzoni1-1/+1
The target and attributes for the PCIe address decoding windows were not correct on Kirkwood for the second PCIe interface. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-09Merge branch 'tegra/clk' into next/dt2Arnd Bergmann27-497/+4936
This is a dependency for the tegra/dt branch. Conflicts: drivers/clocksource/tegra20_timer.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge commit 'v3.9-rc5' into next/clk-exynosKukjin Kim501-3499/+8028
Conflicts: arch/arm/boot/dts/exynos4.dtsi arch/arm/boot/dts/exynos5440.dtsi
2013-04-08clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}Tushar Behera1-4/+4
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: Tushar Behera <tushar.behera@linaro.org> CC: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08clk: exynos4: export clocks required for fimc-isSylwester Nawrocki1-7/+13
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08clk: samsung: Fix compilation errorSachin Kamat1-0/+2
Fixes the below compilation error during non-dt build. drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext': drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration] drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-08video: mxsfb: Introduce regulator supportFabio Estevam1-18/+23
Instead of using a custom binding for retrieving the GPIO that activates the LCD from devicetree, use a standard regulator. This approach has the advantage to be more generic. For example: in the case of a board that has a PMIC supplying the LCD voltage, the current approach would not work, as it only searches for a GPIO pin. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-04clk: tegra: fix enum tegra114_clk to match bindingStephen Warren1-1/+1
A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Remove forced clk_enable of uartdPeter De Schrijver1-1/+1
The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver2-0/+7
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Implement clocks for Tegra114Peter De Schrijver2-0/+2086
Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Workaround for Tegra114 MSENC problemPeter De Schrijver2-0/+11
Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver4-10/+14
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add new fields and PLL types for Tegra114Peter De Schrijver2-1/+888
Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver4-25/+25
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver4-6/+59
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLEPeter De Schrijver2-0/+7
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Add TEGRA_PLL_BYPASS flagPeter De Schrijver2-4/+10
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver4-293/+356
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: provide dummy cpu car opsPeter De Schrijver1-1/+2
tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: defer application of init tableStephen Warren4-2/+25
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2-2/+2
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding2-0/+4
By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Export peripheral reset functionsThierry Reding1-0/+3
The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04clk: tegra: Fix periph_clk_to_bit macroYen Lin1-1/+1
The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into ↵Stephen Warren17-125/+1424
for-3.10/clk
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren3-38/+23
2013-04-04serial: mxs-auart: move to use generic DMA helperShawn Guo1-48/+4
With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04mtd: gpmi: move to use generic DMA helperShawn Guo2-52/+2
With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04i2c: i2c-mxs: move to use generic DMA helperShawn Guo1-37/+3
With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Wolfram Sang <wsa@the-dreams.de>
2013-04-04spi: mxs-spi: move to use generic DMA helperShawn Guo1-51/+9
With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Since mxs is a DT only platform now, along with the changes, the non-DT case handling in probe function also gets removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04mmc: mxs-mmc: move to use generic DMA helperShawn Guo1-43/+5
With the generic DMA device tree helper supported by mxs-dma driver, client devices only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. Since mxs is a DT only platform now, along with the changes, the non-DT case checking in probe function also gets cleaned up. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Chris Ball <cjb@laptop.org> Cc: linux-mmc@vger.kernel.org Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04dma: mxs-dma: move to generic device tree bindingShawn Guo1-4/+66
Update mxs-dma driver to adopt generic DMA device tree binding. It calls of_dma_controller_register() with mxs specific of_dma_xlate to get the generic DMA device tree helper support. Then DMA clients only need to call dma_request_slave_channel() for requesting a DMA channel from dmaengine. The existing way of requesting channel, clients directly call dma_request_channel(), still work there, and will be removed after all mxs-dma clients get converted to generic DMA device tree helper. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04dma: mxs-dma: use devm_* managed functionsShawn Guo1-30/+9
Use devm_* managed functions to simplify probe() error handling. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04video: mxsfb: remove mxsfb_platform_dataShawn Guo1-24/+17
None of mxsfb users uses mxsfb_platform_data now. Let's remove it from mxsfb driver. As the result, include/linux/mxsfb.h gets deleted with a few macros moved into mxsfb.c. Along with the change, the typo "FAILING" in macro name is fixed to be "FALLING". Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-04video: mxsfb: get display timings from device treeShawn Guo2-12/+112
Use videomode helpers to get display timings and configurations from device tree when platform_data is absent. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-04video: mxsfb: remove dotclk_delay from platform_dataShawn Guo1-1/+0
There is no in-tree mxsfb users using mxsfb_platform_data dotclk_delay. Let's remove it from mxsfb_platform_data to ease full device tree adoption of mxsfb driver. If later we have platform/board need to configure this parameter, we can add it into device tree bindings. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-04video: mxsfb: remove fb_phys/fb_size from platform_dataShawn Guo1-32/+7
There is no in-tree users of mxsfb_platform_data fb_phys/fb_size. With CMA support in the kernel, there is no real need for platform to reserve memory and pass address and size into driver via platform_data. So let's remove fb_phys/fb_size from mxsfb_platform_data to ease full device tree adoption. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-04video: mxsfb: use devm_* managed functionsShawn Guo1-34/+16
Use devm_* managed functions to make code a little cleaner. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-04net: freescale: fec: add support for optional enet_out clkWolfram Sang2-0/+11
Some MX28 boards need the internal enet_out clock to be enabled. So, do this in the driver iff the clock was referenced via devicetree. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: David S. Miller <davem@davemloft.net>
2013-04-04net: fec: handle optional clk_ptp more gracefullyShawn Guo1-5/+3
When the optional clk_ptp is absent, we can just set it to NULL, and clk API will just handle it gracefully. It saves us from checking clk_ptp whenever calling into clk API. Also since clk_ptp is optional, the "ret" variable shouldn't be set in case that the clock is absent. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: David S. Miller <davem@davemloft.net>
2013-04-04mmc: davinci_mmc: add DT supportManjunathappa, Prakash1-4/+66
Adds device tree support for davinci_mmc. Also add binding documentation. As of now tested for non-dma PIO mode and without GPIO card_detect/ write_protect option because of dependencies on EDMA and GPIO module DT support. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Cc: linux-mmc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: davinci-linux-open-source@linux.davincidsp.com Cc: devicetree-discuss@lists.ozlabs.org Cc: cjb@laptop.org Cc: Sekhar Nori <nsekhar@ti.com> Cc: mporter@ti.com Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Chris Ball <cjb@laptop.org> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2013-04-04clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala1-1/+9
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add support for SoC-specific register save listTomasz Figa5-8/+39
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Add missing registers to suspend save listTomasz Figa1-0/+33
This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-04-04clk: exynos4: Remove E4X12 prefix from SRC_DMC registerTomasz Figa1-2/+2
This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 10:44:49 +0000