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2017-08-23Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kern...Stephen Boyd14-22/+1452
2017-08-23Merge tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2-12/+19
2017-08-23Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd10-251/+685
2017-08-19clk: sunxi-ng: support R40 SoCIcenowy Zheng4-0/+1365
2017-08-14clk: sunxi-ng: nkm: add support for fixed post-dividerIcenowy Zheng2-3/+21
2017-08-14clk: sunxi-ng: div: Add support for fixed post-dividerPriit Laes2-4/+21
2017-08-10clk: samsung: exynos542x: Enable clock rate propagation up to the EPLLSylwester Nawrocki1-7/+8
2017-08-09clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocksSylwester Nawrocki1-4/+4
2017-08-09clk: samsung: Fix mau_epll clock definition for exynos5422Sylwester Nawrocki1-3/+9
2017-08-04clk: meson: gxbb-aoclk: Add CEC 32k clockNeil Armstrong4-2/+231
2017-08-04clk: meson: gxbb-aoclk: Switch to regmap for register accessNeil Armstrong4-23/+95
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet1-0/+177
2017-08-04clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet1-3/+4
2017-08-04clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet1-1/+2
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl3-13/+156
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clkidsJerome Brunet1-2/+8
2017-08-04clk: meson-gxbb: expose almost every clock in the bindingsJerome Brunet1-110/+7
2017-08-04clk: meson8b: expose every clock in the bindingsJerome Brunet1-99/+4
2017-08-04clk: meson: gxbb: fix protection against undefined clksJerome Brunet1-0/+2
2017-08-04clk: meson: meson8b: fix protection against undefined clksJerome Brunet1-0/+1
2017-08-04clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3Icenowy Zheng1-1/+1
2017-08-04clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai1-0/+11
2017-08-03clk: uniphier: remove sLD3 SoC supportMasahiro Yamada4-45/+20
2017-08-02Merge branch 'clk-fixes' into clk-nextStephen Boyd7-33/+69
2017-08-02clk: keystone: sci-clk: Fix sci_clk_getTero Kristo1-24/+42
2017-08-02Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/...Stephen Boyd1-1/+1
2017-08-02Merge tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-...Stephen Boyd4-0/+18
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet4-0/+18
2017-08-01clk: sunxi-ng: Wait for lock when using fractional modeJernej Škrabec4-4/+8
2017-08-01clk: sunxi-ng: Make fractional helper less chattyJernej Škrabec1-5/+5
2017-08-01clk: sunxi-ng: multiplier: Fix fractional modeJernej Škrabec1-2/+5
2017-08-01clk: sunxi-ng: Fix fractional mode for N-M clocksJernej Škrabec1-2/+14
2017-07-31clk: samsung: exynos5420: The EPLL rate table correctionsSylwester Nawrocki1-8/+8
2017-07-27clk: sunxi-ng: Fix header guard of ccu-sun8i-r.hMatthias Kaehlcke1-1/+1
2017-07-24clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard1-1/+1
2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring25-80/+61
2017-07-21clk: qoriq: add pll clock to clock lookup tableYuantian Tang1-0/+7
2017-07-21clk: qoriq: add clock configuration for ls1088a socYuantian Tang1-0/+12
2017-07-18Merge branch 'clk-fixes' into clk-nextStephen Boyd2-0/+21
2017-07-18clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione1-0/+7
2017-07-17clk: mmp: Drop unnecessary staticJulia Lawall1-1/+1
2017-07-17clk: moxart: remove unnecessary staticsGustavo A. R. Silva1-2/+2
2017-07-17clk: qcom: clk-smd-rpm: Fix the reported rate of branchesGeorgi Djakov1-2/+0
2017-07-17clk: mediatek: fixed static checker warning in clk_cpumux_get_parent callSean Wang1-4/+0
2017-07-17clk: gemini: Fix reset regressionLinus Walleij1-0/+14
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov1-0/+11
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut2-3/+14
2017-07-17clk: vc5: Add support for the input frequency doublerMarek Vasut1-1/+77
2017-07-17clk: vc5: Split clock input mux and predividerMarek Vasut1-12/+34
2017-07-17clk: vc5: Configure the output buffer input mux on prepareMarek Vasut1-0/+19