linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Collapse)	Author	Files	Lines
2013-07-29	usb: phy: omap-usb3: Improve DPLL parameter lookup code	Roger Quadros	1	-49/+38
	Use a mapping table (dpll_map) to match the possible system clock rates to the appropriate DPLL parameters. Introduce a function "omap_usb3_get_dpll_params()" that will return the matching DPLL parameters for the given clock rate. Also, bail out on phy init if DPLL locking fails. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-07-15	usb: phy: omap-usb3: fix dpll clock index	Ruchika Kharwar	1	-1/+1
	Correction of the omap_usb3_dpll_params array when the sys_clk_rate is 20MHz. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-06-01	usb: phy: omap-usb3: updated dpll M,N values to support DRA7xx devices	Ruchika Kharwar	1	-1/+6
	Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
2013-03-18	usb: phy: rename all phy drivers to phy-$name-usb.c	Felipe Balbi	1	-0/+353
	this will make sure that we have sensible names for all phy drivers. Current situation was already quite bad with too generic names being used. Signed-off-by: Felipe Balbi <balbi@ti.com>