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staging
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rtl8723au
/
hal
Age
Commit message (
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Author
Files
Lines
2015-03-06
staging: rtl8723au: odm_ConfigBB_AGC_8723A() always does 32 bit writes
Jes Sorensen
2
-13
/
+6
2015-03-06
staging: rtl8723au: odm.c: Use rtl8723au_{read, write}32() for 32 bit registe...
Jes Sorensen
1
-19
/
+16
2015-03-06
staging: rtl8723au: usb_halinit.c: Use rtl8723au_{read,write}32()
Jes Sorensen
1
-22
/
+21
2015-03-06
staging: rtl8723au: rtl8723a_phycfg.c: Use proper register read/write functions
Jes Sorensen
1
-12
/
+9
2015-03-06
staging: rtl8723au: writeOFDMPowerReg() use rtl8723au_write32()
Jes Sorensen
1
-1
/
+1
2015-03-06
staging: rtl8723au: Clean up PHY_{Query,Set}BBReg() 32 bit read/writes
Jes Sorensen
1
-93
/
+116
2015-03-06
staging: rtl8723au: Reduce the usage of ODM_[GS]et_BBReg()
Jes Sorensen
1
-43
/
+46
2015-03-06
staging: rtl8723au: Remove pointless wrappers around odm_TXPowerTrackingInit()
Jes Sorensen
1
-10
/
+3
2015-03-06
staging: rtl8723au: Remove a number of unused entries from struct dm_odm_t
Jes Sorensen
1
-9
/
+0
2015-03-06
staging: rtl8723au: remove extra parentheses around right bit shift operations
Aya Mahfouz
2
-6
/
+6
2015-03-06
staging: rtl8723au: odm.c: Break some lines down to 80 characters
Jes Sorensen
1
-67
/
+117
2015-03-06
staging: rtl8723au: ODM_Write_DIG23A(): Cosmetic cleanups
Jes Sorensen
1
-7
/
+8
2015-03-06
staging: rtl8723au: Clean up odm_RefreshRateAdaptiveMask()
Jes Sorensen
1
-12
/
+15
2015-03-06
staging: rtl8723au: Clean up FindMinimumRSSI()
Jes Sorensen
1
-6
/
+4
2015-03-06
staging: rtl8723au: Clean up odm_RSSIMonitorCheck()
Jes Sorensen
1
-20
/
+21
2015-03-06
staging: rtl8723au: ODM_TXPowerTrackingCheck23a(): Remove no-op function
Jes Sorensen
1
-20
/
+0
2015-03-06
staging: rtl8723au: Remove write only bIsCurRDLState
Jes Sorensen
1
-1
/
+0
2015-03-06
staging: rtl8723au: Remove unused Funai TV hack
Jes Sorensen
2
-9
/
+0
2015-03-06
staging: rtl8723au: Remove write-only variable ControlChannel
Jes Sorensen
1
-9
/
+0
2015-03-06
staging: rtl8723au: SupportInterface is always set to USB
Jes Sorensen
6
-33
/
+22
2015-03-06
staging: rtl8723au: Remove no-op ODM_CMNINFO_PLATFORM
Jes Sorensen
2
-3
/
+0
2015-03-06
staging: rtl8723au: odm_dtc(): Remove no-op function
Jes Sorensen
1
-7
/
+0
2015-03-06
staging: rtl8723au: Make odm_PHY_SaveAFERegisters() readable
Jes Sorensen
1
-7
/
+2
2015-03-06
staging: rtl8723au: ODM_RF_CALIBRATION is never set
Jes Sorensen
1
-1
/
+1
2015-03-06
staging: rtl8723au: ODM_RF_TX_PWR_TRACK is always set
Jes Sorensen
2
-12
/
+2
2015-03-06
staging: rtl8723au: ODM_BB_PWR_SAVE is unused
Jes Sorensen
1
-2
/
+1
2015-03-06
staging: rtl8723au: ODM_BB_CCK_PD is always set
Jes Sorensen
2
-5
/
+1
2015-03-06
staging: rtl8723au: ODM_BB_RSSI_MONITOR is always set
Jes Sorensen
2
-18
/
+2
2015-03-06
staging: rtl8723au: ODM_BB_FA_CNT is always set
Jes Sorensen
2
-12
/
+2
2015-03-06
staging: rtl8723au: ODM_BB_DYNAMIC_TXPWR isn't used for anything
Jes Sorensen
1
-2
/
+1
2015-03-06
staging: rtl8723au: ODM_BB_DIG is always set
Jes Sorensen
2
-5
/
+3
2015-03-06
staging: rtl8723au: ODM_BB_RA_MASK is always set
Jes Sorensen
2
-16
/
+2
2015-03-06
staging: rtl8723au: ODM_MAC_EDCA_TURBO is always set
Jes Sorensen
2
-4
/
+0
2015-03-06
staging: rtl8723au: Avoid zero initializing variables unnecessarily
Jes Sorensen
1
-2
/
+2
2015-03-06
staging: rtl8723au: Variable bbtchange is always false
Jes Sorensen
1
-2
/
+1
2015-03-06
staging: rtl8723au: rtl8723a_hal_init.c: remove unnecessary braces
Daniele Alessandrelli
1
-26
/
+14
2015-03-06
staging: rtl8723au: MAX_AGGR_NUM is not used
Jes Sorensen
1
-1
/
+0
2015-03-06
staging: rtl8723au: The RF on an 8723au is always a 6052
Jes Sorensen
2
-45
/
+1
2015-03-06
staging: rtl8723au: Remove rf type from struct hal_version
Jes Sorensen
6
-79
/
+13
2015-03-06
staging: rtl8723au: Be more consistent in checking for 2 TX paths
Jes Sorensen
1
-10
/
+8
2015-03-06
staging: rtl8723au: No need for two copies of rf_type
Jes Sorensen
2
-16
/
+3
2015-03-06
staging: rtl8723au: Firmware always handles adaptive rates
Jes Sorensen
1
-12
/
+0
2015-03-06
staging: rtl8723au: rtl8723a_add_rateatid() simplyfy code
Jes Sorensen
1
-4
/
+4
2015-03-06
staging: rtl8723au: rates are always set via the firmware interface
Jes Sorensen
5
-58
/
+18
2015-03-06
staging: rtl8723au: Use RF_AC instead of hardcoded value for RF register write
Jes Sorensen
1
-4
/
+5
2015-02-26
staging: rtl8723au: hal: rewrite the right hand side of an assignment
Aya Mahfouz
1
-2
/
+2
2015-02-26
staging: rtl8723au: hal: rewrite the right hand side of an assignment
Aya Mahfouz
1
-2
/
+2
2015-02-26
staging: rtl8723au: hal: rewrite the right hand side of an assignment
Aya Mahfouz
1
-2
/
+2
2015-02-26
staging: rtl8723au: rewrite the right hand side of an assignment
Aya Mahfouz
1
-1
/
+1
2015-02-26
Staging: rtl8723au: Tabs should be used
Melike Yurtoglu
1
-6
/
+6
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