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2019-04-03staging: add missing SPDX lines to Makefile filesGreg Kroah-Hartman1-0/+1
There are a few remaining drivers/staging/*/Makefile files that do not have SPDX identifiers in them. Add the correct GPL-2.0 identifier to them to make scanning tools happy. Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-24staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP coreJacob Feder1-0/+1
This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder <jacobsfeder@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>