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path: root/drivers/spi/spi-sh-msiof.c
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2021-09-17spi: sh-msiof: drop unneeded MODULE_ALIASKrzysztof Kozlowski1-1/+0
The MODULE_DEVICE_TABLE already creates proper alias for platform driver. Having another MODULE_ALIAS causes the alias to be duplicated. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210916164423.134603-2-krzysztof.kozlowski@canonical.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-06-23spi: spi-sh-msiof: : use proper DMAENGINE API for terminationWolfram Sang1-2/+2
dmaengine_terminate_all() is deprecated in favor of explicitly saying if it should be sync or async. Here, we want dmaengine_terminate_sync() because there is no other synchronization code in the driver to handle an async case. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210623095843.3228-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: sh-msiof: Fill in controller speed limitsGeert Uytterhoeven1-0/+4
Fill in the controller speed limits, so the SPI core can use them for validating SPI transfers, and adjust or reject transfers when needed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210113101916.1147695-3-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: sh-msiof: Fill in spi_transfer.effective_speed_hzGeert Uytterhoeven1-3/+7
Fill in the effective bit rate used for transfers, so the SPI core can calculate instead of estimate delays. Restore "reverse Christmas tree" order of local variables while adding new variables. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210113101916.1147695-2-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-14spi: spi-sh-msiof: Fix checkpatch error Complex macros should use ()Aishwarya R1-1/+1
Fixed checkpatch error "Macros with complex values should be enclosed in parentheses" Signed-off-by: Aishwarya R <raishwar@visteon.com> Link: https://lore.kernel.org/r/20200406155301.21768-1-raishwar@visteon.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-09spi: sh-msiof: Do not redefine STR while compile testingKrzysztof Kozlowski1-209/+209
STR is a well-known stringify macro so it should be avoided in drivers to avoid warnings like this (MIPS architecture while compile testing): drivers/spi/spi-sh-msiof.c:76:0: warning: "STR" redefined #define STR 0x40 /* Status Register */ arch/mips/include/asm/mipsregs.h:30:0: note: this is the location of the previous definition #define STR(x) __STR(x) To maintain consistency between all register names add a SI prefix to all of them. This also matches register names in datasheet. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200108194319.3171-1-krzk@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-07spi: sh-msiof: Convert to generic unused native cs handling.Geert Uytterhoeven1-50/+3
Currently the MSIOF SPI driver uses custom code to handle the unused native chip select with GPIO chip selects. Convert the driver to use the new generic handling in the SPI core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200102133822.29346-3-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07spi: sh-msiof: Use devm_platform_ioremap_resource() helperGeert Uytterhoeven1-3/+1
Use the devm_platform_ioremap_resource() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20190807085213.24666-1-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-02spi: Remove dev_err() usage after platform_get_irq()Stephen Boyd1-1/+0
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-28spi: sh-msiof: Reduce delays in sh_msiof_modify_ctr_wait()Geert Uytterhoeven1-1/+1
While the Hardware User Manual does not document the maximum time needed for modifying bits in the MSIOF Control Register, experiments on R-Car Gen2/Gen3 and SH-Mobile AG5 revealed the following typical modification times for the various bits: - CTR.TXE and CTR.RXE: no delay, - CTR.TSCKE: less than 10 ns, - CTR.TFSE: up to a few hundred ns (depending on SPI transfer clock, i.e. less for faster transfers). There are no reasons to believe these figures are different for SH-MobileR2 SoCs (SH7723/SH7724). Hence the minimum busy-looping delay of 10 µs is excessive. Reduce the delay per loop iteration from 10 to 1 us, and the maximum delay from 1000 to 100 µs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-04spi: sh-msiof: Convert to use GPIO descriptorsGeert Uytterhoeven1-16/+4
Convert GPIO chip selects in the Renesas MSIOF SPI driver from legacy GPIO numbers to GPIO descriptors. Notes: - The board file for the SH7724-based Ecovec24 development board now registers a GPIO descriptor lookup, instead of passing a GPIO number through controller_data, - sh_msiof_get_cs_gpios() must release all GPIOs, else spi_get_gpio_descs() cannot claim them during SPI controller registration. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-03spi: sh-msiof: Add reset of registers before starting transferGeert Uytterhoeven1-0/+18
In accordance with hardware specification Ver 1.0, reset register transmission / reception setting before transfer. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> [geert: Use readl_poll_timeout_atomic()] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-03spi: sh-msiof: Use readl_poll_timeout_atomic() instead of open-codingGeert Uytterhoeven1-9/+3
Replace the open-coded loop in sh_msiof_modify_ctr_wait() by a call to the readl_poll_timeout_atomic() helper macro. Suggested-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-03spi: sh-msiof: Use BIT() and GENMASK()Geert Uytterhoeven1-87/+87
Improve maintainability by converting the register bit, bitmask, and bitfield definitions from hexadecimal constants to constructs using BIT(), GENMASK(), or "val << shift". Suggested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-04spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3Geert Uytterhoeven1-1/+7
While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support bits-per-word values in the full range 8..32, the variants present in R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32. Obtain the value from family-specific sh_msiof_chipdata to fix this. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08spi: sh-msiof: Replace spi_master by spi_controllerGeert Uytterhoeven1-85/+83
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-18spi: sh-msiof: Use DMA if possibleHoan Nguyen An1-6/+2
Currently, this driver only supports feature for DMA 32-bits. In this case, only if the data length is divisible by 4 to use DMA, otherwise PIO will be used. This patch will suggest use the DMA 32-bits with 4bytes of words, then the remaining data will be transmitted by PIO mode. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-18spi: sh-msiof: fix *info pointer in request_dma()Hoan Nguyen An1-1/+1
sh_msiof_spi_info *info struct pointer was initialized in the probe() function no need to get back and keep consistency. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-12-20spi: sh-msiof: Reduce the number of times write to and perform the ↵Hoan Nguyen An1-1/+9
transmission from FIFO The current state of the spi-sh-msiof, in master transfer mode: if t-> bits_per_word <= 8, if the data length is divisible by 4 ((len & 3) = 0), the length of each word will be 32 bits In case of data length can not be divisible by 4 ((len & 3) != 0), always set each word to be 8 bits, this will increase the number of times that write to FIFO, increasing the number of times it should be transmitted. Assume that the number of bytes of data length more than 64 bytes, each transmission will write 64 times into the TFDR then transmit, a maximum one-time transmission will transmit 64 bytes if each word is 8 bits long. Switch to setting if t->bits_per_word <= 8, the word length will be 32 bits although the data length is not divisible by 4, then if leftover, will transmit the balance and the length of each words is 1 byte. The maximum each can transmit up to 64 x 4 (Data Size = 32 bits (4 bytes)) = 256 bytes. TMDR2 : Bits 28 to 24 BITLEN1[4:0] Data Size (8 to 32 bits) Bits 23 to 16 WDLEN1[7:0] Word Count (1 to 64 words) Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-11-05spi: spi-sh-msiof: simplify getting .driver_dataWolfram Sang1-4/+2
We should get 'driver_data' from 'struct device' directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-21Merge branch 'spi-4.20' into spi-nextMark Brown1-5/+1
2018-10-15spi: sh-msiof: fix deferred probingSergei Shtylyov1-2/+2
Since commit 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq") platform_get_irq() can return -EPROBE_DEFER. However, the driver overrides an error returned by that function with -ENOENT which breaks the deferred probing. Propagate upstream an error code returned by platform_get_irq() and remove the bogus "platform" from the error message, while at it... Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-09-05spi: sh-msiof: Fix handling of write value for SISTR registerHiromitsu Yamasaki1-1/+2
This patch changes writing to the SISTR register according to the H/W user's manual. The TDREQ bit and RDREQ bits of SISTR are read-only, and must be written their initial values of zero. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> [geert: reword] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2018-09-05spi: sh-msiof: Fix invalid SPI use during system suspendGaku Inami1-0/+25
If the SPI queue is running during system suspend, the system may lock up. Fix this by stopping/restarting the queue during system suspend/resume by calling spi_master_suspend()/spi_master_resume() from the PM callbacks. In-kernel users will receive an -ESHUTDOWN error while system suspend/resume is in progress. Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> [geert: Cleanup, reword] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2018-08-28spi: use SPDX identifier for Renesas driversWolfram Sang1-5/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-06-18spi: sh-msiof: Make sure all DMA operations have completedGeert Uytterhoeven1-24/+29
In case of a bi-directional transfer, receive DMA may complete in the rcar-dmac driver before transmit DMA, due to scheduling latencies. As the MSIOF driver waits for completion of the receive DMA only, it may submit the next transmit DMA request before the previous one has completed. Make the driver more robust by waiting for the completion of both receive and transmit DMA, when applicable. Based on a patch in the BSP by Ryo Kataoka. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-06-04Merge branch 'spi-4.17' into spi-4.18 for the merge windowMark Brown1-2/+4
2018-05-24spi: sh-msiof: Fix setting SIRMDR1.SYNCAC to match SITMDR1.SYNCACGeert Uytterhoeven1-2/+4
According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit must match the value of the SITMDR1.SYNCAC bit. However, sh_msiof_spi_setup() changes only the latter. Fix this by updating the SIRMDR1 register like the SITMDR1 register, taking into account register bits that exist in SITMDR1 only. Reported-by: Renesas BSP team via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from spi_master.setup()") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-04-17spi: sh-msiof: Simplify calculation of divisors for transfer rateVladimir Zapolskiy1-32/+35
The change updates sh_msiof_spi_set_clk_regs() function by iterating over BRDV power values. Note that the change is a functional one, namely prescaler output x 1/1 set in BRDV bit field (0b111) for MSO division rate set to 2 is substituted by BRDV = 0b000 and BRPS = 0b0, in terms of written values to TSCR setting of 0x0107 is substituted by 0x0000, and for all input parameter cases this is the only functional change, which touches the controller. As a result of the rework the function is supposed to be slightly more efficient and more readable and maintainable in case of any further extensions. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-04-16spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCRVladimir Zapolskiy1-0/+1
The change fixes a bit field overflow which allows to write to higher bits while calculating SPI transfer clock and setting BRPS and BRDV bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz' ratio is greater than 1024, for instance p->min_div = 2, MSO rate = 33333333, SPI device rate = 10000 results in k = 5, i.e. BRDV = 0b100 or 1/32 prescaler output, BRPS = 105, TSCR value = 0x6804, thus MSSEL and MSIMM bit fields are non-zero. Fixes: 65d5665bb260 ("spi: sh-msiof: Update calculation of frequency dividing") Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-03-22spi: sh-msiof: Use correct enum for DMA transfer directionGeert Uytterhoeven1-2/+2
Use enum dma_transfer_direction as required by dmaengine_prep_slave_sg() instead of enum dma_data_direction. This won't change behavior in practice as the enum values are equivalent. This fixes two warnings when building with clang: drivers/spi/spi-sh-msiof.c:755:27: warning: implicit conversion from enumeration type 'enum dma_data_direction' to different enumeration type 'enum dma_transfer_direction' [-Wenum-conversion] rx->sgl, rx->nents, DMA_FROM_DEVICE, ^~~~~~~~~~~~~~~ drivers/spi/spi-sh-msiof.c:772:27: warning: implicit conversion from enumeration type 'enum dma_data_direction' to different enumeration type 'enum dma_transfer_direction' [-Wenum-conversion] tx->sgl, tx->nents, DMA_TO_DEVICE, ^~~~~~~~~~~~~ Based on commit 768d59f5d0139a6f ("spi: rspi: use correct enum for DMA transfer direction"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-26Merge remote-tracking branches 'spi/topic/pxa2xx', 'spi/topic/s3c64xx', ↵Mark Brown1-22/+94
'spi/topic/sh-msiof', 'spi/topic/sirf' and 'spi/topic/sun6i' into spi-next
2018-01-03spi: sh-msiof: Fix timeout failures for TX-only DMA transfersGeert Uytterhoeven1-1/+11
When using RX (with or without TX), the DMA interrupt triggers completion when the RX FIFO has been emptied, i.e. after the full transfer has finished. However, when using TX without RX, the DMA interrupt triggers completion as soon as the DMA engine has filled the TX FIFO, i.e. before the full transfer has finished. Then sh_msiof_modify_ctr_wait() will spin until the transfer has really finished and the TFSE bit is cleared, for at most 1 ms. For slow speeds and/or large transfers, this may cause timeouts and transfer failures: spi_sh_msiof e6e10000.spi: failed to shut down hardware 74x164 spi2.0: SPI transfer failed: -110 spi_master spi2: failed to transfer one message from queue 74x164 spi2.0: Failed writing: -110 Fix this by waiting explicitly until the TX FIFO has been emptied. Based on a patch in the BSP by Hiromitsu Yamasaki. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-14spi: sh-msiof: Implement cs-gpios configurationGeert Uytterhoeven1-7/+59
The current support for GPIO chip selects assumes the GPIOs have been configured by platform code or the boot loader. This includes pinmux setup and GPIO direction. Hence it does not work as expected when just described in DT using the "cs-gpios" property. Fix this by: 1. using devm_gpiod_get_index() to request the GPIO, and thus configure pinmux, if needed, 2. configuring the GPIO direction is the spi_master.setup() callback. Use gpio_is_valid() instead of a check on positive numbers. Note that when using GPIO chip selects, at least one native chip select must be left unused, as that native chip select will be driven anyway, and (global) native chip select polarity must be taken into account. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-14spi: sh-msiof: Extend support to 3 native chip selectsGeert Uytterhoeven1-5/+13
Currently only the MSIOF_SYNC signal can be used as a native chip select. Extend support to up to 3 native chipselects using the MSIOF_SS1 and MSIOF_SS2 signals. Inspired by a patch in the BSP by Hiromitsu Yamasaki. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-12-14spi: sh-msiof: Avoid writing to registers from spi_master.setup()Geert Uytterhoeven1-11/+24
The spi_master.setup() callback must not change configuration registers, as that could corrupt I/O that is in progress for other SPI slaves. The only exception is the configuration of the native chip select polarity in SPI master mode, as a wrong chip select polarity will cause havoc during all future transfers to any other SPI slave. Hence stop writing to registers in sh_msiof_spi_setup(), unless it is the first call for a controller using a native chip select, or unless native chip select polarity has changed (note that you'll loose anyway if I/O is in progress). Even then, only do what is strictly necessary, instead of calling sh_msiof_spi_set_pin_regs(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-30spi: sh-msiof: Use dev_warn_once() instead of open-codingGeert Uytterhoeven1-3/+2
Use the helper introduced by commit e135303bd5bebcd2 ("device: Add dev_<level>_once variants") instead of open-coding the same functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-10Merge remote-tracking branches 'spi/topic/sh-msiof', 'spi/topic/slave', ↵Mark Brown1-6/+4
'spi/topic/spreadtrum' and 'spi/topic/tegra114' into spi-next
2017-11-03spi: sh-msiof: remove redundant pointer devColin Ian King1-2/+0
The pointer dev is assigned but never read, hence it is redundant and can be removed. Cleans up clang warning: drivers/spi/spi-sh-msiof.c:1198:2: warning: Value stored to 'dev' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-02spi: sh-msiof: Fix DMA transfer size checkHiromitsu Yamasaki1-1/+1
DMA supports 32-bit words only, even if BITLEN1 of SITMDR2 register is 16bit. Fixes: b0d0ce8b6b91 ("spi: sh-msiof: Add DMA support") Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-10-04spi: sh-msiof: Use of_device_get_match_data() helperGeert Uytterhoeven1-4/+2
Use the of_device_get_match_data() helper instead of open coding. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-25spi: sh-msiof: Add compatible strings for r8a774[35]Fabrizio Castro1-0/+2
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-07-17spi: sh-msiof: Limit minimum divider on R-Car Gen3Geert Uytterhoeven1-9/+23
On R-Car Gen3 SoCs (excluding R-Car H3 ES1.x, which cannot be used for SPI due to a hardware erratum), BRPS x BRDV = 1/1 is an invalid divider setting. Implement this limitation using an SoC/family-specific minimum divider. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-05-26spi: sh-msiof: Add slave mode supportHisashi Nakamura1-33/+78
Add slave mode support to the MSIOF driver, in both PIO and DMA mode. For now this only supports the transmission of messages with a size that is known in advance. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> [geert: Timeout handling cleanup, spi core integration, cancellation, rewording] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-01-04spi: sh-msiof: Remove useless memory allocation failure messageGeert Uytterhoeven1-3/+1
Printing an error on memory allocation failure is unnecessary. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-20spi: sh-msiof: Do not use C++ style commentSimon Horman1-1/+1
4286db8456f4 ("spi: sh-msiof: Add R-Car Gen 2 and 3 fallback bindings") added a C++ style comment. This is not in keeping with the style used for comments elsewhere in this fine. Update it accordingly. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-14spi: sh-msiof: Add R-Car Gen 2 and 3 fallback bindingsSimon Horman1-1/+3
In the case of Renesas R-Car hardware we know that there are generations of SoCs, e.g. Gen 2 and Gen 3. But beyond that it's not clear what the relationship between IP blocks might be. For example, I believe that r8a7790 is older than r8a7791 but that doesn't imply that the latter is a descendant of the former or vice versa. We can, however, by examining the documentation and behaviour of the hardware at run-time observe that the current driver implementation appears to be compatible with the IP blocks on SoCs within a given generation. For the above reasons and convenience when enabling new SoCs a per-generation fallback compatibility string scheme is being adopted for drivers for Renesas SoCs. Also: * Deprecate renesas,sh-msiof. It seems poorly named as it is only compatible with SH-Mobile. It also appears unused in mainline. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-21spi: sh-msiof: Add support for R-Car M3-WGeert Uytterhoeven1-0/+1
MSIOF in R-Car M3-W (r8a7796) is handled fine by the existing driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-05spi: sh-msiof: Avoid invalid clock generator parametersGeert Uytterhoeven1-0/+3
The conversion from a look-up table to a calculation for clock generator parameters forgot to take into account that BRDV x 1/1 is valid only if BRPS is x 1/1 or x 1/2, leading to undefined behavior (e.g. arbitrary clock rates). This limitation is documented for the MSIOF module in all supported SH/R-Mobile and R-Car Gen2/Gen3 ARM SoCs. Tested on r8a7791/koelsch and r8a7795/salvator-x. Fixes: 65d5665bb260b034 ("spi: sh-msiof: Update calculation of frequency dividing") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-06-22spi: sh-msiof: Remove sh_msiof_spi_priv.chipdataGeert Uytterhoeven1-9/+9
After probe time, the pointer to the sh_msiof_chipdata structure in the sh_msiof_spi_priv structure is used only for checking the SPI master flags. As these are also available in the spi_master structure, convert the users to access those, and remove the pointer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
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