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2015-09-01Merge tag 'armsoc-drivers' of ↵Linus Torvalds22-448/+3616
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - memory controller work for ARM's PL172 memory controller - reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits) ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile memory: tegra: Add Tegra210 support memory: tegra: Add support for a variable-size client ID bitfield clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver ...
2015-08-20Merge tag 'tegra-for-4.3-soc' of ↵Olof Johansson14-448/+830
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers ARM: tegra: Core SoC changes for v4.3-rc1 This contains a bit more of Tegra210 support, which is shaping up pretty nicely. Other than that there are a couple of cleanup patches here, too. * tag 'tegra-for-4.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile soc/tegra: fuse: Add spare bit offset for Tegra210 soc/tegra: fuse: Add spare bit offset for Tegra124 soc/tegra: fuse: Add spare bit offset for Tegra114 soc/tegra: fuse: Rename core_* to soc_* soc/tegra: fuse: Add Tegra210 support soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers soc/tegra: fuse: Restrict legacy code to 32-bit ARM soc/tegra: pmc: Add Tegra210 support soc/tegra: pmc: Restrict legacy code to 32-bit ARM soc/tegra: pmc: Avoid usage of uninitialized variable soc/tegra: Add Tegra210 support soc/tegra: Add Tegra132 support Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-13soc/tegra: pmc: Use existing pclk referenceThierry Reding1-9/+7
The driver requests the pclk clock at probe time already and stores its reference to it in struct tegra_pmc, so there is no need to look it up everytime it is needed. Use the existing reference instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13soc/tegra: pmc: Remove unnecessary return statementThierry Reding1-1/+0
Functions returning no value don't need an explicit return statement. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in MakefileMasahiro Yamada1-3/+3
Kbuild descends into drivers/soc/tegra/ only when CONFIG_ARCH_TEGRA is enabled. (see drivers/soc/Makefile) $(CONFIG_ARCH_TEGRA) in drivers/soc/tegra/Makefile always evaluates to 'y'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13Merge tag 'qcom-soc-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm ↵Olof Johansson5-0/+2372
into next/drivers Qualcomm ARM Based SoC Updates for 4.3 * Add SMEM driver * Add SMD driver * Add RPM over SMD driver * Select QCOM_SCM by default * tag 'qcom-soc-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm: devicetree: soc: Add Qualcomm SMD based RPM DT binding soc: qcom: Driver for the Qualcomm RPM over SMD soc: qcom: Add Shared Memory Driver soc: qcom: Add device tree binding for Shared Memory Device drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PM soc: qcom: Add Shared Memory Manager driver Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-05ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resetsRussell King3-0/+414
The PMU device contains an interrupt controller, power control and resets. The interrupt controller is a little sub-standard in that there is no race free way to clear down pending interrupts, so we try to avoid problems by reducing the window as much as possible, and clearing as infrequently as possible. The interrupt support is implemented using an IRQ domain, and the parent interrupt referenced in the standard DT way. The power domains and reset support is closely related - there is a defined sequence for powering down a domain which is tightly coupled with asserting the reset. Hence, it makes sense to group these two together, and in order to avoid any locking contention disrupting this sequence, we avoid the use of syscon or regmap. This patch adds the core PMU driver: power domains must be defined in the DT file in order to make use of them. The reset controller can be referenced in the standard way for reset controllers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-08-05soc: mediatek: Fix SCPSYS compilationMatthias Brugger1-0/+1
SCPSYS driver misses the module.h include which makes it fail when compiling with allmodconf. This patch fixes this. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-07-29soc: qcom: Driver for the Qualcomm RPM over SMDBjorn Andersson3-0/+259
Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based devices. The driver exposes resources that child drivers can operate on; to implementing regulator, clock and bus frequency drivers. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-29soc: qcom: Add Shared Memory DriverBjorn Andersson3-0/+1328
This adds the Qualcomm Shared Memory Driver (SMD) providing communication channels to remote processors, ontop of SMEM. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-28drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PMLina Iyer1-0/+1
Enable QCOM_SCM for QCOM power management driver Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-28soc: qcom: Add Shared Memory Manager driverBjorn Andersson3-0/+784
The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-16soc/tegra: fuse: Add spare bit offset for Tegra210Thierry Reding1-0/+1
The offset of the first spare bit register on Tegra210 is 0x380, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: fuse: Add spare bit offset for Tegra124Thierry Reding1-0/+1
The offset of the first spare bit register on Tegra124 is 0x300, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: fuse: Add spare bit offset for Tegra114Thierry Reding1-0/+1
The offset of the first spare bit register on Tegra114 is 0x280, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: fuse: Rename core_* to soc_*Thierry Reding7-44/+44
There's a mixture of core_* and soc_* prefixes for variables storing information related to the VDD_CORE rail. Choose one (soc_*) and use it more consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: fuse: Add Tegra210 supportThierry Reding5-1/+212
Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: fuse: Unify Tegra20 and Tegra30 driversThierry Reding10-367/+413
Unifying the drivers makes it easier to restrict the legacy probing paths to 32-bit ARM. This in turn will come in handy as support for new 64-bit ARM SoCs is added. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: fuse: Restrict legacy code to 32-bit ARMThierry Reding1-9/+58
For backwards-compatibility with old device trees, if no APBMISC node exists this driver hard-codes the I/O memory region. All 64-bit ARM device tree files are recent enough that they can be required to have this node, and therefore the legacy code path is not required. Based on work done by Paul Walmsley <pwalmsley@nvidia.com>. Cc: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: pmc: Add Tegra210 supportThierry Reding1-0/+48
Tegra210 uses a power management controller that is compatible with earlier SoC generations but adds a couple of power partitions for new hardware blocks. Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: pmc: Restrict legacy code to 32-bit ARMThierry Reding1-15/+41
For backwards-compatibility with old device trees, if no PMC node exists this driver hard-codes the I/O memory region. All 64-bit ARM device tree files are recent enough that they can be required to have this node, and therefore the legacy code path is not required on 64-bit ARM. Based on work done by Paul Walmsley <pwalmsley@nvidia.com>. Cc: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: pmc: Avoid usage of uninitialized variableThierry Reding1-2/+2
Make sure to only drop the reference to the OF node after it's been successfully obtained. Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC") Cc: <stable@vger.kernel.org> # v4.0+ Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: Add Tegra210 supportThierry Reding1-0/+1
Add Tegra210 to the matching table for NVIDIA Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16soc/tegra: Add Tegra132 supportThierry Reding1-0/+1
Add Tegra132 to the matching table for NVIDIA Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-10soc: mediatek: Drop owner assignment from platform_driverKrzysztof Kozlowski1-1/+0
platform_driver does not need to set an owner because platform_driver_register() will set it. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-07-06soc: Mediatek: Add SCPSYS power domain driverSascha Hauer3-0/+498
This adds a power domain driver for the Mediatek SCPSYS unit. The System Control Processor System (SCPSYS) has several power management related tasks in the system. The tasks include thermal measurement, dynamic voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control. The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power domain control. For now this driver only adds power domain support, the more advanced features are not yet supported. The driver implements the generic PM domain device tree bindings, the first user will most likely be the Mediatek AFE audio driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-07-06soc: mediatek: Add infracfg misc driver supportSascha Hauer3-0/+101
This adds support for some miscellaneous bits of the infracfg controller. The mtk_infracfg_set/clear_bus_protection functions are necessary for the scpsys power domain driver to handle the bus protection bits which are contained in the infacfg register space. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-07-02Merge tag 'armsoc-late' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late fixes and dependencies from Kevin Hilman: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. Other than the fixes, the primary feature being added is the conversion of some OMAP drivers to the new generic wakeirq interface" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: multi_v7_defconfig: Enable BRCMNAND driver ARM: BCM: Do not select CONFIG_MTD_NAND_BRCMNAND ARM: at91/dt: update udc compatible strings ARM: at91/dt: trivial: fix USB udc compatible string arm64: dts: Add APM X-Gene standby GPIO controller DTS entries soc: qcom: spm: Fix idle on THUMB2 kernels ARM: dove: fix legacy dove IRQ numbers ARM: mvebu: fix suspend to RAM on big-endian configurations ARM: mvebu: adjust Armada XP DT spi muxing after pinctrl function rename serial: 8250_omap: Move wake-up interrupt to generic wakeirq serial: omap: Switch wake-up interrupt to generic wakeirq mmc: omap_hsmmc: Change wake-up interrupt to use generic wakeirq
2015-07-02Merge tag 'module-builtin_driver-v4.1-rc8' of ↵Linus Torvalds2-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux Pull module_platform_driver replacement from Paul Gortmaker: "Replace module_platform_driver with builtin_platform driver in non modules. We see an increasing number of non-modular drivers using modular_driver() type register functions. There are several downsides to letting this continue unchecked: - The code can appear modular to a reader of the code, and they won't know if the code really is modular without checking the Makefile and Kconfig to see if compilation is governed by a bool or tristate. - Coders of drivers may be tempted to code up an __exit function that is never used, just in order to satisfy the required three args of the modular registration function. - Non-modular code ends up including the <module.h> which increases CPP overhead that they don't need. - It hinders us from performing better separation of the module init code and the generic init code. So here we introduce similar macros for builtin drivers. Then we convert builtin drivers (controlled by a bool Kconfig) by making the following type of mapping: module_platform_driver() ---> builtin_platform_driver() module_platform_driver_probe() ---> builtin_platform_driver_probe(). The set of drivers that are converted here are just the ones that showed up as relying on an implicit include of <module.h> during a pending header cleanup. So we convert them here vs adding an include of <module.h> to non-modular code to avoid compile fails. Additonal conversions can be done asynchronously at any time. Once again, an unused module_exit function that is removed here appears in the diffstat as an outlier wrt all the other changes" * tag 'module-builtin_driver-v4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: drivers/clk: convert sunxi/clk-mod0.c to use builtin_platform_driver drivers/power: Convert non-modular syscon-reboot to use builtin_platform_driver drivers/soc: Convert non-modular soc-realview to use builtin_platform_driver drivers/soc: Convert non-modular tegra/pmc to use builtin_platform_driver drivers/cpufreq: Convert non-modular s5pv210-cpufreq.c to use builtin_platform_driver drivers/cpuidle: Convert non-modular drivers to use builtin_platform_driver drivers/platform: Convert non-modular pdev_bus to use builtin_platform_driver platform_device: better support builtin boilerplate avoidance
2015-07-01soc: qcom: spm: Fix idle on THUMB2 kernelsStephen Boyd1-1/+1
The ifc6410 firmware always enters the kernel in ARM state from deep idle. Use the cpu_resume_arm() wrapper instead of cpu_resume() to property switch into the THUMB2 state when we wake up from idle. This fixes a problem reported by Kevin Hilman on next-20150601 where the ifc6410 fails to boot a THUMB2 kernel because the platform's firmware always enters the kernel in ARM mode from deep idle states. Reported-by: Kevin Hilman <khilman@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-26Merge tag 'armsoc-drivers' of ↵Linus Torvalds9-0/+711
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ...
2015-06-26Merge tag 'armsoc-soc' of ↵Linus Torvalds2-8/+21
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform support updates from Kevin Hilman: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits) ARM: zx: Add basic defconfig support for ZX296702 ARM: dts: zx: add an initial zx296702 dts and doc clk: zx: add clock support to zx296702 dt-bindings: Add #defines for ZTE ZX296702 clocks ARM: socfpga: fix build error due to secondary_startup MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS ARM: ep93xx: simone: support for SPI-based MMC/SD cards MAINTAINERS: update Shawn's email to use kernel.org one ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: EXYNOS: register power domain driver from core_initcall ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs ARM: SAMSUNG: Constify platform_device_id ARM: EXYNOS: Constify irq_domain_ops ARM: EXYNOS: add coupled cpuidle support for Exynos3250 ARM: EXYNOS: add exynos_get_boot_addr() helper ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ...
2015-06-24Merge tag 'armsoc-drivers' into test-mergeKevin Hilman9-0/+711
ARM: SoC: driver updates for v4.2 Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses Conflicts: arch/arm64/boot/dts/arm/juno-motherboard.dtsi Trivial add/add conflict with our dt branch. Resolution: take both sides. # gpg: Signature made Wed Jun 24 21:32:17 2015 PDT using RSA key ID D3FBC665 # gpg: Good signature from "Kevin Hilman <khilman@deeprootsystems.com>" # gpg: aka "Kevin Hilman <khilman@linaro.org>" # gpg: aka "Kevin Hilman <khilman@kernel.org>" # Conflicts: # arch/arm64/boot/dts/arm/juno-motherboard.dtsi
2015-06-24Merge tag 'armsoc-soc' into test-mergeKevin Hilman2-8/+21
ARM: SoC: platform support for v4.2 Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC Conflicts: arch/arm/mach-socfpga/core.h Trivial remove/remove conflict with our cleanup branch. Resolution: remove both sides # gpg: Signature made Wed Jun 24 21:32:12 2015 PDT using RSA key ID D3FBC665 # gpg: Good signature from "Kevin Hilman <khilman@deeprootsystems.com>" # gpg: aka "Kevin Hilman <khilman@linaro.org>" # gpg: aka "Kevin Hilman <khilman@kernel.org>" # Conflicts: # arch/arm/mach-socfpga/core.h
2015-06-16drivers/soc: Convert non-modular soc-realview to use builtin_platform_driverPaul Gortmaker1-1/+1
This file depends on Kconfig SOC_REALVIEW which is a bool, so we use the appropriate registration function, which avoids us relying on an implicit inclusion of <module.h> which we are doing currently. While this currently works, we really don't want to be including the module.h header in non-modular code, which we'd be forced to do, pending some upcoming code relocation from init.h into module.h. So we fix it now by using the non-modular equivalent. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: Axel Lin <axel.lin@ingics.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-16drivers/soc: Convert non-modular tegra/pmc to use builtin_platform_driverPaul Gortmaker1-1/+1
This file depends on Kconfig ARCH_TEGRA which is a bool, so we use the appropriate registration function, which avoids us relying on an implicit inclusion of <module.h> which we are doing currently. While this currently works, we really don't want to be including the module.h header in non-modular code, which we'd be forced to do, pending some upcoming code relocation from init.h into module.h. So we fix it now by using the non-modular equivalent. Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2015-06-01drivers: soc: sunxi: Introduce SoC driver to map SRAMsMaxime Ripard5-0/+297
The Allwinner SoCs have a handful of SRAM that can be either mapped to be accessible by devices or the CPU. That mapping is controlled by an SRAM controller, and that mapping might not be set by the bootloader, for example if the device wasn't used at all, or if we're using solutions like the U-Boot's Falcon Boot. We could also imagine changing this at runtime for example to change the mapping of these SRAMs to use them for suspend/resume or runtime memory rate change, if that ever happens. These use cases require some API in the kernel to control that mapping, exported through a drivers/soc driver. This driver also implement a debugfs file that shows the SRAM found in the system, the current mapping and the SRAM that have been claimed by some drivers in the kernel. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-29Merge tag 'qcom-soc-for-4.2-1' of ↵Arnd Bergmann3-0/+393
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/drivers Merge "Qualcomm ARM Based SoC Updates for v4.2-1" from Kumar Gala: * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code * Added HDCP SCM call * tag 'qcom-soc-for-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: firmware: qcom: scm: Add HDCP Support firmware: qcom: scm: Split out 32-bit specific SCM code ARM: qcom: Add Subsystem Power Manager (SPM) driver
2015-05-29Merge tag 'v4.1-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann2-45/+10
next/drivers Merge "ARM: mediatek: soc updates for v4.2" from Matthias Brugger: - pmic wrapper: fix clock handling - pmic wrapper: fix state machine - pmic wrapper: fix compile dependency * tag 'v4.1-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: Add compile dependency to pmic-wrapper soc: mediatek: PMIC wrap: Fix register state machine handling soc: mediatek: PMIC wrap: Fix clock rate handling
2015-05-27soc: mediatek: Add compile dependency to pmic-wrapperMatthias Brugger1-0/+1
The pmic-wrapper calls the reset controller. If CONFIG_RESET_CONTROLLER is not set, compilation fails with: drivers/soc/mediatek/mtk-pmic-wrap.c: In function ‘pwrap_probe’: drivers/soc/mediatek/mtk-pmic-wrap.c:836:2: error: implicit declaration of function ‘devm_reset_control_get’ [-Werror=implicit-function-declaration] This patch sets the dependency in the Kconfig file. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-27soc: mediatek: PMIC wrap: Fix register state machine handlingSascha Hauer1-10/+2
When the PMIC wrapper state machine has read a register it goes into the "wait for valid clear" (vldclr) state. The state machine stays in this state until the VLDCLR bit is written to. We should write this bit after reading a register because the SCPSYS won't let the system go into suspend as long as the state machine waits for valid clear. Since now we never leave the state machine in vldclr state we no longer have to check for this state on pwrap_read/pwrap_write entry and can remove the corresponding code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-27soc: mediatek: PMIC wrap: Fix clock rate handlingSascha Hauer1-35/+7
replace chipselect extension values based on SPI clock with hardcoded SoC specific values. The PMIC wrapper has the ability of extending the chipselects by configurable amounts of time. We configured the values based on the rate of SPI clock, but this is wrong. The delays should be configured based on the internal PMIC clock that latches the values from the SPI bus to the internal PMIC registers. By default this clock is 24MHz. Other clock frequencies are for debugging only and can be removed from the driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-04soc/tegra: pmc: move to using a restart handlerDavid Riley1-6/+17
The pmc driver was previously exporting tegra_pmc_restart, which was assigned to machine_desc.init_machine, taking precedence over the restart handlers registered through register_restart_handler(). Signed-off-by: David Riley <davidriley@chromium.org> [tomeu.vizoso@collabora.com: Rebased] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> [treding@nvidia.com: minor cleanups] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-04soc/tegra: fuse: Add RAM code reader helperMikko Perttunen1-0/+21
Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-04soc/tegra: Watch wait_for_completion_timeout() return typeNicholas Mc Guire1-2/+4
The return type of the wait_for_completion_timeout() function is not int but unsigned long. An appropriately named unsigned long is added and the assignment fixed up. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-27ARM: qcom: Add Subsystem Power Manager (SPM) driverLina Iyer3-0/+393
SPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode. The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence. Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode. Add support for an idle driver to set up the SPM to place the core in Standby or Standalone power collapse mode when the core is idle. Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>, Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org> Original tree available at - git://codeaurora.org/quic/la/kernel/msm-3.10.git Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Kevin Hilman <khilman@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Kumar Gala <galak@codeaurora.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-04-14Merge tag 'v4.0-next-soc-fix' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann1-2/+0
next/drivers Merge "fix unused variable warning for pmic-wrapper" from Matthias Brugger * tag 'v4.0-next-soc-fix' of https://github.com/mbgg/linux-mediatek: soc/mediatek: Remove unused variables
2015-04-13soc/mediatek: Remove unused variablesThierry Reding1-2/+0
The PMIC wrapper driver adds a couple of variables that are never used. Remove them to avoid build warnings. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-04-03Merge tag 'v4.0-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson5-0/+991
next/drivers Merge "ARM: mediatek: soc updates for v4.1" from Matthias Brugger: - enable the pin controller in Kconfig - Add PMIC wrapper for MT8135 and MT8173 SoCs * tag 'v4.0-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs ARM: mediatek: enable the pin controller Signed-off-by: Olof Johansson <olof@lixom.net>
2015-03-30soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCsFlora Fu5-0/+991
This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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